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7366e19379
Move IPQ5018 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing and maintenance easier. New schema is equivalent to the old one with few changes: - Adding a required compatible, which is actually redundant. - Drop the really obvious comments next to clock/reg/reset-names items. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251217-dt-bindings-pci-qcom-v2-5-873721599754@oss.qualcomm.com
190 lines
5.2 KiB
YAML
190 lines
5.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq5018.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm IPQ5018 PCI Express Root Complex
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Manivannan Sadhasivam <mani@kernel.org>
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properties:
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compatible:
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enum:
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- qcom,pcie-ipq5018
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reg:
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minItems: 5
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maxItems: 6
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reg-names:
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minItems: 5
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items:
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- const: dbi
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- const: elbi
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- const: atu
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- const: parf
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- const: config
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- const: mhi
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clocks:
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maxItems: 6
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clock-names:
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items:
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- const: iface # PCIe to SysNOC BIU clock
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- const: axi_m # AXI Master clock
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- const: axi_s # AXI Slave clock
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- const: ahb
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- const: aux
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- const: axi_bridge
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interrupts:
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maxItems: 9
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interrupt-names:
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items:
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- const: msi0
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- const: msi1
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- const: msi2
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- const: msi3
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- const: msi4
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- const: msi5
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- const: msi6
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- const: msi7
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- const: global
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resets:
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maxItems: 8
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reset-names:
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items:
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- const: pipe
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- const: sleep
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- const: sticky # Core sticky reset
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- const: axi_m # AXI master reset
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- const: axi_s # AXI slave reset
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- const: ahb
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- const: axi_m_sticky # AXI master sticky reset
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- const: axi_s_sticky # AXI slave sticky reset
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required:
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- resets
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- reset-names
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allOf:
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- $ref: qcom,pcie-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
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pcie@a0000000 {
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compatible = "qcom,pcie-ipq5018";
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reg = <0xa0000000 0xf1d>,
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<0xa0000f20 0xa8>,
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<0xa0001000 0x1000>,
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<0x00080000 0x3000>,
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<0xa0100000 0x1000>,
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<0x00083000 0x1000>;
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reg-names = "dbi",
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"elbi",
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"atu",
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"parf",
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"config",
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"mhi";
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ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>,
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<0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>;
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device_type = "pci";
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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num-lanes = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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/* The controller supports Gen3, but the connected PHY is Gen2-capable */
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max-link-speed = <2>;
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clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
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<&gcc GCC_PCIE0_AXI_M_CLK>,
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<&gcc GCC_PCIE0_AXI_S_CLK>,
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<&gcc GCC_PCIE0_AHB_CLK>,
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<&gcc GCC_PCIE0_AUX_CLK>,
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<&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>;
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clock-names = "iface",
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"axi_m",
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"axi_s",
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"ahb",
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"aux",
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"axi_bridge";
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msi-map = <0x0 &v2m0 0x0 0xff8>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0",
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"msi1",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7",
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"global";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&pcie0_phy>;
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phy-names = "pciephy";
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resets = <&gcc GCC_PCIE0_PIPE_ARES>,
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<&gcc GCC_PCIE0_SLEEP_ARES>,
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<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
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<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
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<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
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<&gcc GCC_PCIE0_AHB_ARES>,
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<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
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<&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
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reset-names = "pipe",
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"sleep",
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"sticky",
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"axi_m",
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"axi_s",
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"ahb",
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"axi_m_sticky",
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"axi_s_sticky";
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perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>;
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pcie@0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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bus-range = <0x01 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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