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The Cadence I2C controller has an external reset that needs to be de-asserted before the I2C controller can be accessed. Document the `resets` devicetree property that can be used to describe how the reset signal is connected. While the reset signal will always be present in hardware the devicetree property is kept optional for backwards compatibility with existing systems that do not specify the reset property and where the reset signal might not be controlled by operating system. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
73 lines
1.4 KiB
YAML
73 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cadence I2C controller
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maintainers:
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- Michal Simek <michal.simek@xilinx.com>
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allOf:
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- $ref: /schemas/i2c/i2c-controller.yaml#
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properties:
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compatible:
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enum:
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- cdns,i2c-r1p10 # cadence i2c controller version 1.0
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- cdns,i2c-r1p14 # cadence i2c controller version 1.4
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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resets:
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maxItems: 1
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interrupts:
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maxItems: 1
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clock-frequency:
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minimum: 1
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maximum: 400000
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description: |
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Desired operating frequency, in Hz, of the bus.
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clock-name:
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const: pclk
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description: |
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Input clock name.
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fifo-depth:
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description:
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Size of the data FIFO in bytes.
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 16
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enum: [2, 4, 8, 16, 32, 64, 128, 256]
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required:
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- compatible
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- reg
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- clocks
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- interrupts
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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i2c@e0004000 {
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compatible = "cdns,i2c-r1p10";
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clocks = <&clkc 38>;
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resets = <&rstc 288>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xe0004000 0x1000>;
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clock-frequency = <400000>;
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#address-cells = <1>;
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#size-cells = <0>;
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fifo-depth = <8>;
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};
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