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The Allwinner A523 SoC family has a second Ethernet controller, called the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for numbering. This controller, according to BSP sources, is fully compatible with a slightly newer version of the Synopsys DWMAC core. The glue layer around the controller is the same as found around older DWMAC cores on Allwinner SoCs. The only slight difference is that since this is the second controller on the SoC, the register for the clock delay controls is at a different offset. Last, the integration includes a dedicated clock gate for the memory bus and the whole thing is put in a separately controllable power domain. Add a compatible string entry for it, and work in the requirements for a second clock and a power domain. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Link: https://patch.msgid.link/20250925191600.3306595-2-wens@kernel.org Signed-off-by: Paolo Abeni <pabeni@redhat.com>
418 lines
9.8 KiB
YAML
418 lines
9.8 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A83t EMAC
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <mripard@kernel.org>
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# We need a select here so we don't match all nodes with 'snps,dwmac'
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select:
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properties:
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compatible:
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contains:
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enum:
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- allwinner,sun8i-a83t-emac
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- allwinner,sun8i-h3-emac
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- allwinner,sun8i-r40-gmac
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- allwinner,sun8i-v3s-emac
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- allwinner,sun50i-a64-emac
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- allwinner,sun55i-a523-gmac200
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required:
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- compatible
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properties:
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compatible:
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oneOf:
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- const: allwinner,sun8i-a83t-emac
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- const: allwinner,sun8i-h3-emac
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- const: allwinner,sun8i-r40-gmac
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- const: allwinner,sun8i-v3s-emac
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- const: allwinner,sun50i-a64-emac
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- items:
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- enum:
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- allwinner,sun20i-d1-emac
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- allwinner,sun50i-a100-emac
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- allwinner,sun50i-h6-emac
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- allwinner,sun50i-h616-emac0
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- allwinner,sun55i-a523-gmac0
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- const: allwinner,sun50i-a64-emac
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- items:
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- const: allwinner,sun55i-a523-gmac200
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- const: snps,dwmac-4.20a
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-names:
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const: macirq
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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items:
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- const: stmmaceth
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- const: mbus
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phy-supply:
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description: PHY regulator
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power-domains:
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maxItems: 1
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syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the device containing the EMAC or GMAC clock
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register
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- resets
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- reset-names
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- phy-handle
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- phy-mode
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- syscon
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allOf:
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- $ref: snps,dwmac.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- allwinner,sun8i-a83t-emac
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- allwinner,sun8i-h3-emac
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- allwinner,sun8i-v3s-emac
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- allwinner,sun50i-a64-emac
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then:
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properties:
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allwinner,tx-delay-ps:
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default: 0
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minimum: 0
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maximum: 700
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multipleOf: 100
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description:
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External RGMII PHY TX clock delay chain value in ps.
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allwinner,rx-delay-ps:
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default: 0
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minimum: 0
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maximum: 3100
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multipleOf: 100
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description:
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External RGMII PHY TX clock delay chain value in ps.
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- if:
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properties:
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compatible:
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contains:
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enum:
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- allwinner,sun8i-r40-gmac
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then:
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properties:
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allwinner,rx-delay-ps:
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default: 0
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minimum: 0
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maximum: 700
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multipleOf: 100
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description:
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External RGMII PHY TX clock delay chain value in ps.
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- if:
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properties:
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compatible:
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contains:
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enum:
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- allwinner,sun8i-h3-emac
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- allwinner,sun8i-v3s-emac
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then:
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properties:
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allwinner,leds-active-low:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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EPHY LEDs are active low.
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mdio-mux:
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type: object
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unevaluatedProperties: false
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properties:
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compatible:
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const: allwinner,sun8i-h3-mdio-mux
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mdio-parent-bus:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to EMAC MDIO.
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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mdio@1:
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$ref: mdio.yaml#
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unevaluatedProperties: false
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description: Internal MDIO Bus
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properties:
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compatible:
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const: allwinner,sun8i-h3-mdio-internal
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reg:
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const: 1
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patternProperties:
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"^ethernet-phy@[0-9a-f]$":
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type: object
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$ref: ethernet-phy.yaml#
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unevaluatedProperties: false
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description:
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Integrated PHY node
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properties:
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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required:
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- clocks
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- resets
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mdio@2:
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$ref: mdio.yaml#
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unevaluatedProperties: false
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description: External MDIO Bus (H3 only)
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properties:
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reg:
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const: 2
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required:
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- compatible
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- mdio-parent-bus
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- mdio@1
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- if:
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properties:
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compatible:
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contains:
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const: allwinner,sun55i-a523-gmac200
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then:
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properties:
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clocks:
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minItems: 2
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clock-names:
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minItems: 2
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tx-internal-delay-ps:
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default: 0
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minimum: 0
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maximum: 700
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multipleOf: 100
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description:
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External RGMII PHY TX clock delay chain value in ps.
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rx-internal-delay-ps:
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default: 0
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minimum: 0
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maximum: 3100
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multipleOf: 100
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description:
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External RGMII PHY TX clock delay chain value in ps.
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required:
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- power-domains
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else:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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maxItems: 1
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power-domains: false
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unevaluatedProperties: false
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examples:
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- |
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ethernet@1c0b000 {
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compatible = "allwinner,sun8i-h3-emac";
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syscon = <&syscon>;
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reg = <0x01c0b000 0x104>;
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interrupts = <0 82 1>;
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interrupt-names = "macirq";
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resets = <&ccu 12>;
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reset-names = "stmmaceth";
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clocks = <&ccu 27>;
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clock-names = "stmmaceth";
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phy-handle = <&int_mii_phy>;
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phy-mode = "mii";
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allwinner,leds-active-low;
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mdio1: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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};
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mdio-mux {
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compatible = "allwinner,sun8i-h3-mdio-mux";
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#address-cells = <1>;
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#size-cells = <0>;
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mdio-parent-bus = <&mdio1>;
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int_mii_phy: mdio@1 {
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compatible = "allwinner,sun8i-h3-mdio-internal";
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-phy@1 {
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reg = <1>;
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clocks = <&ccu 67>;
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resets = <&ccu 39>;
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phy-is-integrated;
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};
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};
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mdio@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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- |
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ethernet@1c0b000 {
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compatible = "allwinner,sun8i-h3-emac";
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syscon = <&syscon>;
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reg = <0x01c0b000 0x104>;
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interrupts = <0 82 1>;
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interrupt-names = "macirq";
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resets = <&ccu 12>;
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reset-names = "stmmaceth";
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clocks = <&ccu 27>;
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clock-names = "stmmaceth";
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phy-handle = <&ext_rgmii_phy>;
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phy-mode = "rgmii";
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allwinner,leds-active-low;
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mdio2: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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};
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mdio-mux {
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compatible = "allwinner,sun8i-h3-mdio-mux";
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#address-cells = <1>;
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#size-cells = <0>;
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mdio-parent-bus = <&mdio2>;
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mdio@1 {
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compatible = "allwinner,sun8i-h3-mdio-internal";
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-phy@1 {
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reg = <1>;
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clocks = <&ccu 67>;
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resets = <&ccu 39>;
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};
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};
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mdio@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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ext_rgmii_phy: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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};
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- |
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ethernet@1c0b000 {
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compatible = "allwinner,sun8i-a83t-emac";
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syscon = <&syscon>;
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reg = <0x01c0b000 0x104>;
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interrupts = <0 82 1>;
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interrupt-names = "macirq";
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resets = <&ccu 13>;
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reset-names = "stmmaceth";
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clocks = <&ccu 27>;
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clock-names = "stmmaceth";
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phy-handle = <&ext_rgmii_phy1>;
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phy-mode = "rgmii";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ext_rgmii_phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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- |
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ethernet@4510000 {
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compatible = "allwinner,sun55i-a523-gmac200",
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"snps,dwmac-4.20a";
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reg = <0x04510000 0x10000>;
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clocks = <&ccu 117>, <&ccu 79>;
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clock-names = "stmmaceth", "mbus";
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resets = <&ccu 43>;
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reset-names = "stmmaceth";
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interrupts = <0 47 4>;
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interrupt-names = "macirq";
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii1_pins>;
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power-domains = <&pck600 4>;
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syscon = <&syscon>;
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phy-handle = <&ext_rgmii_phy_1>;
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phy-mode = "rgmii-id";
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snps,fixed-burst;
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snps,axi-config = <&gmac1_stmmac_axi_setup>;
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ext_rgmii_phy_1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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...
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