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149009f2dc
The binding for Qualcomm SoC UFS controllers grew and it will grow
further. Split SM8650 and SM8750 UFS controllers which:
1. Do not reference ICE as IO address space, but as phandle,
2. Have same order of clocks.
3. Have MCQ I/O address space. Document that MCQ address space as
optional to maintain backwards compatibility and because Linux
drivers can operate perfectly fine without it (thus without MCQ
feature). Linux driver already uses "mcq" as possible name for
"reg-names" property.
The split allows easier review and maintenance of the binding.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250731-dt-bindings-ufs-qcom-v2-3-53bb634bf95a@linaro.org
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
244 lines
6.2 KiB
YAML
244 lines
6.2 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Universal Flash Storage (UFS) Controller
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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- Andy Gross <agross@kernel.org>
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# Select only our matches, not all jedec,ufs-2.0
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select:
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properties:
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compatible:
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contains:
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enum:
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- qcom,msm8994-ufshc
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- qcom,msm8996-ufshc
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- qcom,qcs615-ufshc
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- qcom,sdm845-ufshc
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- qcom,sm6115-ufshc
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- qcom,sm6125-ufshc
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- qcom,sm6350-ufshc
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- qcom,sm8150-ufshc
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- qcom,msm8994-ufshc
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- qcom,msm8996-ufshc
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- qcom,qcs615-ufshc
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- qcom,sdm845-ufshc
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- qcom,sm6115-ufshc
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- qcom,sm6125-ufshc
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- qcom,sm6350-ufshc
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- qcom,sm8150-ufshc
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- const: qcom,ufshc
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- const: jedec,ufs-2.0
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qcom,ice:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the Inline Crypto Engine node
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reg:
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minItems: 1
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maxItems: 2
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reg-names:
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items:
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- const: std
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- const: ice
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required:
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- compatible
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- reg
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allOf:
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- $ref: qcom,ufs-common.yaml
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sdm845-ufshc
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- qcom,sm6350-ufshc
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- qcom,sm8150-ufshc
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then:
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properties:
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clocks:
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minItems: 9
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maxItems: 9
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clock-names:
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items:
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- const: core_clk
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- const: bus_aggr_clk
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- const: iface_clk
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- const: core_clk_unipro
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- const: ref_clk
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- const: tx_lane0_sync_clk
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- const: rx_lane0_sync_clk
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- const: rx_lane1_sync_clk
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- const: ice_core_clk
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reg:
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minItems: 2
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maxItems: 2
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reg-names:
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minItems: 2
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required:
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- reg-names
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,msm8996-ufshc
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then:
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properties:
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clocks:
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minItems: 9
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maxItems: 9
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clock-names:
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items:
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- const: core_clk
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- const: bus_clk
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- const: bus_aggr_clk
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- const: iface_clk
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- const: core_clk_unipro
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- const: core_clk_ice
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- const: ref_clk
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- const: tx_lane0_sync_clk
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- const: rx_lane0_sync_clk
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reg:
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minItems: 1
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maxItems: 1
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reg-names:
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maxItems: 1
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,qcs615-ufshc
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- qcom,sm6115-ufshc
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- qcom,sm6125-ufshc
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then:
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properties:
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clocks:
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minItems: 8
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maxItems: 8
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clock-names:
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items:
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- const: core_clk
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- const: bus_aggr_clk
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- const: iface_clk
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- const: core_clk_unipro
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- const: ref_clk
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- const: tx_lane0_sync_clk
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- const: rx_lane0_sync_clk
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- const: ice_core_clk
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reg:
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minItems: 2
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maxItems: 2
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reg-names:
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minItems: 2
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required:
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- reg-names
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# TODO: define clock bindings for qcom,msm8994-ufshc
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- if:
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required:
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- qcom,ice
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then:
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properties:
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reg:
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maxItems: 1
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clocks:
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minItems: 7
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maxItems: 8
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else:
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properties:
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reg:
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minItems: 1
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maxItems: 2
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clocks:
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minItems: 7
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maxItems: 9
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm8150.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,sm8150.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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ufs@1d84000 {
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compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
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"jedec,ufs-2.0";
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reg = <0x0 0x01d84000 0x0 0x2500>,
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<0x0 0x01d90000 0x0 0x8000>;
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reg-names = "std", "ice";
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&ufs_mem_phy_lanes>;
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phy-names = "ufsphy";
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lanes-per-direction = <2>;
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#reset-cells = <1>;
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resets = <&gcc GCC_UFS_PHY_BCR>;
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reset-names = "rst";
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reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
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vcc-supply = <&vreg_l7b_2p5>;
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vcc-max-microamp = <1100000>;
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vccq-supply = <&vreg_l9b_1p2>;
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vccq-max-microamp = <1200000>;
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power-domains = <&gcc UFS_PHY_GDSC>;
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iommus = <&apps_smmu 0x300 0>;
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clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
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<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
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<&gcc GCC_UFS_PHY_AHB_CLK>,
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<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
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<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
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clock-names = "core_clk",
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"bus_aggr_clk",
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"iface_clk",
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"core_clk_unipro",
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"ref_clk",
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"tx_lane0_sync_clk",
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"rx_lane0_sync_clk",
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"rx_lane1_sync_clk",
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"ice_core_clk";
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freq-table-hz = <37500000 300000000>,
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<0 0>,
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<0 0>,
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<37500000 300000000>,
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<0 0>,
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<0 0>,
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<0 0>,
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<0 0>,
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<0 300000000>;
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};
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};
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