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Add debug nodes, "dgfx_pkg_residencies" for G-states (G2, G6, G8, G10, ModS) and "dgfx_pcie_link_residencies" for PCIe link states(L0, L1, L1.2) residency counters. v1: - Expose all G-State residency counter values under dgfx_pkg_residencies. (Anshuman) - Include runtime_get/put. (Riana) v2: - Move offset macros to drm/xe/regs/xe_pmt. (Riana) v3: - Include debugfs node "dgfx_pcie_link_residencies" for pcie link residency counter values. (Anshuman) v4: - Include check for BMG and add helper function for repetitive code. (Riana) - Add for loop and local struct to avoid repetition. (Riana) - Use "drm_debugfs_create_files" to create debugfs. (Karthik) v5: - Reorder commits to reflect the correct dependency hierarchy. (Jonathan) - Simplification of commit message and rectified register offset.(Karthik) - Error handling and return before printing. (Riana) v6: - Remove check for DGFX as BMG is discrete. (Karthik) - Rearrange residency offsets in ascending order. (Riana) v7: - Squash the macros into the patch they are used in. (Lucas) Signed-off-by: Soham Purkait <soham.purkait@intel.com> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Reviewed-by: Karthik Poosa <karthik.poosa@intel.com> Reviewed-by: Riana Tauro <riana.tauro@intel.com> Link: https://lore.kernel.org/r/20250716101412.3062780-2-soham.purkait@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
35 lines
1017 B
C
35 lines
1017 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2024 Intel Corporation
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*/
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#ifndef _XE_PMT_H_
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#define _XE_PMT_H_
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#include "xe_regs.h"
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#define BMG_PMT_BASE_OFFSET 0xDB000
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#define BMG_DISCOVERY_OFFSET (SOC_BASE + BMG_PMT_BASE_OFFSET)
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#define PUNIT_TELEMETRY_GUID XE_REG(BMG_DISCOVERY_OFFSET + 0x4)
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#define BMG_ENERGY_STATUS_PMT_OFFSET (0x30)
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#define ENERGY_PKG REG_GENMASK64(31, 0)
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#define ENERGY_CARD REG_GENMASK64(63, 32)
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#define BMG_TELEMETRY_BASE_OFFSET 0xE0000
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#define BMG_TELEMETRY_OFFSET (SOC_BASE + BMG_TELEMETRY_BASE_OFFSET)
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#define SG_REMAP_INDEX1 XE_REG(SOC_BASE + 0x08)
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#define SG_REMAP_BITS REG_GENMASK(31, 24)
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#define BMG_MODS_RESIDENCY_OFFSET (0x4D0)
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#define BMG_G2_RESIDENCY_OFFSET (0x530)
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#define BMG_G6_RESIDENCY_OFFSET (0x538)
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#define BMG_G8_RESIDENCY_OFFSET (0x540)
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#define BMG_G10_RESIDENCY_OFFSET (0x548)
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#define BMG_PCIE_LINK_L0_RESIDENCY_OFFSET (0x570)
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#define BMG_PCIE_LINK_L1_RESIDENCY_OFFSET (0x578)
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#define BMG_PCIE_LINK_L1_2_RESIDENCY_OFFSET (0x580)
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#endif
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