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Document the device tree bindings for the DWC3 USB controller found in Google Tensor SoCs, starting with the G5 generation (codename: laguna). The Tensor G5 silicon represents a complete architectural departure from previous generations (like gs101), including entirely new clock/reset schemes, top-level wrapper and register interface. Consequently, existing Samsung/Exynos DWC3 USB bindings are incompatible, necessitating this new device tree binding. The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features Dual-Role Device single port with hibernation support. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Roy Luo <royluo@google.com> Link: https://patch.msgid.link/20251218-controller-v10-1-4047c9077274@google.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>