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3ec5c15793
Add basic DisplayPort audio support. Support non-live audio playback from two PCMs (DMA channels), and the volume control in the audio mixer. As older dtb files may not have the audio DMA channels defined, the driver will just mark the audio support as disabled if the audio DMA is missing, and will continue with only display support. Note: Reset doesn't seem to work (ZYNQMP_DISP_AUD_SOFT_RESET). If we do a reset, audio playback won't start again even if, afaics, we do set up all the necessary registers. So, at the moment, resetting the audio block in dp_dai_hw_free() is commented out. Tested-by: Anatoliy Klymenko <anatoliy.klymenko@amd.com> Reviewed-by: Vishal Sagar <vishal.sagar@amd.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241023-xilinx-dp-audio-v4-3-5128881457be@ideasonboard.com
99 lines
2.4 KiB
C
99 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* ZynqMP DPSUB Subsystem Driver
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*
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* Copyright (C) 2017 - 2020 Xilinx, Inc.
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*
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* Authors:
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* - Hyun Woo Kwon <hyun.kwon@xilinx.com>
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* - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*/
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#ifndef _ZYNQMP_DPSUB_H_
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#define _ZYNQMP_DPSUB_H_
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#include <linux/types.h>
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struct clk;
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struct device;
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struct drm_bridge;
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struct zynqmp_disp;
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struct zynqmp_disp_layer;
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struct zynqmp_dp;
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struct zynqmp_dpsub_drm;
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#define ZYNQMP_DPSUB_NUM_LAYERS 2
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enum zynqmp_dpsub_port {
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ZYNQMP_DPSUB_PORT_LIVE_VIDEO,
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ZYNQMP_DPSUB_PORT_LIVE_GFX,
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ZYNQMP_DPSUB_PORT_LIVE_AUDIO,
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ZYNQMP_DPSUB_PORT_OUT_VIDEO,
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ZYNQMP_DPSUB_PORT_OUT_AUDIO,
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ZYNQMP_DPSUB_PORT_OUT_DP,
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ZYNQMP_DPSUB_NUM_PORTS,
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};
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enum zynqmp_dpsub_format {
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ZYNQMP_DPSUB_FORMAT_RGB,
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ZYNQMP_DPSUB_FORMAT_YCRCB444,
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ZYNQMP_DPSUB_FORMAT_YCRCB422,
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ZYNQMP_DPSUB_FORMAT_YONLY,
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};
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struct zynqmp_dpsub_audio;
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/**
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* struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem
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* @dev: The physical device
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* @apb_clk: The APB clock
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* @vid_clk: Video clock
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* @vid_clk_from_ps: True of the video clock comes from PS, false from PL
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* @aud_clk: Audio clock
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* @aud_clk_from_ps: True of the audio clock comes from PS, false from PL
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* @connected_ports: Bitmask of connected ports in the device tree
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* @dma_enabled: True if the DMA interface is enabled, false if the DPSUB is
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* driven by the live input
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* @drm: The DRM/KMS device data
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* @bridge: The DP encoder bridge
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* @disp: The display controller
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* @layers: Video and graphics layers
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* @dp: The DisplayPort controller
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* @dma_align: DMA alignment constraint (must be a power of 2)
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*/
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struct zynqmp_dpsub {
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struct device *dev;
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struct clk *apb_clk;
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struct clk *vid_clk;
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bool vid_clk_from_ps;
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struct clk *aud_clk;
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bool aud_clk_from_ps;
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unsigned int connected_ports;
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bool dma_enabled;
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struct zynqmp_dpsub_drm *drm;
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struct drm_bridge *bridge;
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struct zynqmp_disp *disp;
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struct zynqmp_disp_layer *layers[ZYNQMP_DPSUB_NUM_LAYERS];
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struct zynqmp_dp *dp;
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unsigned int dma_align;
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struct zynqmp_dpsub_audio *audio;
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};
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#ifdef CONFIG_DRM_ZYNQMP_DPSUB_AUDIO
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int zynqmp_audio_init(struct zynqmp_dpsub *dpsub);
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void zynqmp_audio_uninit(struct zynqmp_dpsub *dpsub);
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#else
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static inline int zynqmp_audio_init(struct zynqmp_dpsub *dpsub) { return 0; }
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static inline void zynqmp_audio_uninit(struct zynqmp_dpsub *dpsub) { }
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#endif
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void zynqmp_dpsub_release(struct zynqmp_dpsub *dpsub);
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#endif /* _ZYNQMP_DPSUB_H_ */
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