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8a25c4be58
Start using device specific parameters instead of module parameters for most things. The module parameters become the immutable initial values for i915 parameters. The device specific parameters in i915->params start life as a copy of i915_modparams. Any later changes are only reflected in the debugfs. The stragglers are: * i915.force_probe and i915.modeset. Needed before dev_priv is available. This is fine because the parameters are read-only and never modified. * i915.verbose_state_checks. Passing dev_priv to I915_STATE_WARN and I915_STATE_WARN_ON would result in massive and ugly churn. This is handled by not exposing the parameter via debugfs, and leaving the parameter writable in sysfs. This may be fixed up in follow-up work. * i915.inject_probe_failure. Only makes sense in terms of the module, not the device. This is handled by not exposing the parameter via debugfs. v2: Fix uc i915 lookup code (Michał Winiarski) Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com> Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com> Cc: Michał Winiarski <michal.winiarski@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Michał Winiarski <michal.winiarski@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20200618150402.14022-1-jani.nikula@intel.com
174 lines
4.7 KiB
C
174 lines
4.7 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*/
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#include "gem/i915_gem_mman.h"
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#include "gt/intel_engine_user.h"
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#include "i915_drv.h"
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#include "i915_perf.h"
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int i915_getparam_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct drm_i915_private *i915 = to_i915(dev);
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const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
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drm_i915_getparam_t *param = data;
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int value;
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switch (param->param) {
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case I915_PARAM_IRQ_ACTIVE:
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case I915_PARAM_ALLOW_BATCHBUFFER:
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case I915_PARAM_LAST_DISPATCH:
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case I915_PARAM_HAS_EXEC_CONSTANTS:
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/* Reject all old ums/dri params. */
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return -ENODEV;
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case I915_PARAM_CHIPSET_ID:
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value = i915->drm.pdev->device;
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break;
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case I915_PARAM_REVISION:
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value = i915->drm.pdev->revision;
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break;
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case I915_PARAM_NUM_FENCES_AVAIL:
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value = i915->ggtt.num_fences;
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break;
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case I915_PARAM_HAS_OVERLAY:
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value = !!i915->overlay;
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break;
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case I915_PARAM_HAS_BSD:
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value = !!intel_engine_lookup_user(i915,
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I915_ENGINE_CLASS_VIDEO, 0);
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break;
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case I915_PARAM_HAS_BLT:
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value = !!intel_engine_lookup_user(i915,
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I915_ENGINE_CLASS_COPY, 0);
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break;
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case I915_PARAM_HAS_VEBOX:
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value = !!intel_engine_lookup_user(i915,
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I915_ENGINE_CLASS_VIDEO_ENHANCE, 0);
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break;
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case I915_PARAM_HAS_BSD2:
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value = !!intel_engine_lookup_user(i915,
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I915_ENGINE_CLASS_VIDEO, 1);
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break;
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case I915_PARAM_HAS_LLC:
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value = HAS_LLC(i915);
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break;
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case I915_PARAM_HAS_WT:
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value = HAS_WT(i915);
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break;
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case I915_PARAM_HAS_ALIASING_PPGTT:
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value = INTEL_PPGTT(i915);
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break;
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case I915_PARAM_HAS_SEMAPHORES:
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value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
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break;
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case I915_PARAM_HAS_SECURE_BATCHES:
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value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN);
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break;
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case I915_PARAM_CMD_PARSER_VERSION:
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value = i915_cmd_parser_get_version(i915);
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break;
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case I915_PARAM_SUBSLICE_TOTAL:
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value = intel_sseu_subslice_total(sseu);
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if (!value)
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return -ENODEV;
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break;
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case I915_PARAM_EU_TOTAL:
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value = sseu->eu_total;
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if (!value)
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return -ENODEV;
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break;
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case I915_PARAM_HAS_GPU_RESET:
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value = i915->params.enable_hangcheck &&
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intel_has_gpu_reset(&i915->gt);
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if (value && intel_has_reset_engine(&i915->gt))
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value = 2;
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break;
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case I915_PARAM_HAS_RESOURCE_STREAMER:
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value = 0;
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break;
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case I915_PARAM_HAS_POOLED_EU:
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value = HAS_POOLED_EU(i915);
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break;
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case I915_PARAM_MIN_EU_IN_POOL:
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value = sseu->min_eu_in_pool;
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break;
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case I915_PARAM_HUC_STATUS:
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value = intel_huc_check_status(&i915->gt.uc.huc);
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if (value < 0)
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return value;
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break;
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case I915_PARAM_MMAP_GTT_VERSION:
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/* Though we've started our numbering from 1, and so class all
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* earlier versions as 0, in effect their value is undefined as
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* the ioctl will report EINVAL for the unknown param!
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*/
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value = i915_gem_mmap_gtt_version();
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break;
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case I915_PARAM_HAS_SCHEDULER:
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value = i915->caps.scheduler;
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break;
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case I915_PARAM_MMAP_VERSION:
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/* Remember to bump this if the version changes! */
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case I915_PARAM_HAS_GEM:
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case I915_PARAM_HAS_PAGEFLIPPING:
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case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
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case I915_PARAM_HAS_RELAXED_FENCING:
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case I915_PARAM_HAS_COHERENT_RINGS:
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case I915_PARAM_HAS_RELAXED_DELTA:
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case I915_PARAM_HAS_GEN7_SOL_RESET:
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case I915_PARAM_HAS_WAIT_TIMEOUT:
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case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
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case I915_PARAM_HAS_PINNED_BATCHES:
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case I915_PARAM_HAS_EXEC_NO_RELOC:
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case I915_PARAM_HAS_EXEC_HANDLE_LUT:
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case I915_PARAM_HAS_COHERENT_PHYS_GTT:
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case I915_PARAM_HAS_EXEC_SOFTPIN:
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case I915_PARAM_HAS_EXEC_ASYNC:
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case I915_PARAM_HAS_EXEC_FENCE:
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case I915_PARAM_HAS_EXEC_CAPTURE:
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case I915_PARAM_HAS_EXEC_BATCH_FIRST:
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case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
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case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
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/* For the time being all of these are always true;
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* if some supported hardware does not have one of these
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* features this value needs to be provided from
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* INTEL_INFO(), a feature macro, or similar.
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*/
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value = 1;
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break;
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case I915_PARAM_HAS_CONTEXT_ISOLATION:
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value = intel_engines_has_context_isolation(i915);
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break;
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case I915_PARAM_SLICE_MASK:
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value = sseu->slice_mask;
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if (!value)
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return -ENODEV;
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break;
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case I915_PARAM_SUBSLICE_MASK:
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value = sseu->subslice_mask[0];
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if (!value)
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return -ENODEV;
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break;
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case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
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value = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz;
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break;
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case I915_PARAM_MMAP_GTT_COHERENT:
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value = INTEL_INFO(i915)->has_coherent_ggtt;
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break;
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case I915_PARAM_PERF_REVISION:
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value = i915_perf_ioctl_version();
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break;
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default:
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DRM_DEBUG("Unknown parameter %d\n", param->param);
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return -EINVAL;
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}
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if (put_user(value, param->value))
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return -EFAULT;
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return 0;
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}
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