Files
linux/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
Sergio Paracuellos adb2424d0d dt-bindings: clock: add clock definitions for Ralink SoCs
Add clock missing definitions for RT2880, RT305X, RT3352, RT3383, RT5350,
MT7620 and MT76X8 Ralink SoCs. Update bindings to clarify clock depending
on these new introduced constants so consumer nodes can easily use the
correct one in DTS files matching properly what is being used in driver
code (clock IDs are implicitly used there).

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2025-02-21 18:03:09 +01:00

74 lines
1.8 KiB
YAML

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MTMIPS SoCs System Controller
maintainers:
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
description: |
MediaTek MIPS and Ralink SoCs provides a system controller to allow
to access to system control registers. These registers include clock
and reset related ones so this node is both clock and reset provider
for the rest of the world.
These SoCs have an XTAL from where the cpu clock is
provided as well as derived clocks for the bus and the peripherals.
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifiers could be found in:
[1]: <include/dt-bindings/clock/mediatek,mtmips-sysc.h>.
properties:
compatible:
items:
- enum:
- ralink,mt7620-sysc
- ralink,mt7628-sysc
- ralink,mt7688-sysc
- ralink,rt2880-sysc
- ralink,rt3050-sysc
- ralink,rt3052-sysc
- ralink,rt3352-sysc
- ralink,rt3883-sysc
- ralink,rt5350-sysc
- const: syscon
reg:
maxItems: 1
'#clock-cells':
description:
The first cell indicates the clock number, see [1] for available
clocks.
const: 1
'#reset-cells':
description:
The first cell indicates the reset bit within the register.
const: 1
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
syscon@0 {
compatible = "ralink,rt5350-sysc", "syscon";
reg = <0x0 0x100>;
#clock-cells = <1>;
#reset-cells = <1>;
};