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0fe53c0ab0
The child nodes are missing "additionalProperties" constraints which
means any undocumented properties or child nodes are allowed. Add the
constraints, and fix the fallout of wrong manager node regex and
missing properties.
Fixes: 9c1de033af ("dt-bindings: net: pse-pd: Add bindings for PD692x0 PSE controller")
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Kory Maincent <kory.maincent@bootlin.com>
Link: https://lore.kernel.org/r/20240523171732.2836880-1-robh@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
177 lines
3.9 KiB
YAML
177 lines
3.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/pse-pd/microchip,pd692x0.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip PD692x0 Power Sourcing Equipment controller
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maintainers:
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- Kory Maincent <kory.maincent@bootlin.com>
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allOf:
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- $ref: pse-controller.yaml#
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properties:
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compatible:
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enum:
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- microchip,pd69200
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- microchip,pd69210
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- microchip,pd69220
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reg:
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maxItems: 1
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managers:
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type: object
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additionalProperties: false
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description:
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List of the PD69208T4/PD69204T4/PD69208M PSE managers. Each manager
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have 4 or 8 physical ports according to the chip version. No need to
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specify the SPI chip select as it is automatically detected by the
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PD692x0 PSE controller. The PSE managers have to be described from
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the lowest chip select to the greatest one, which is the detection
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behavior of the PD692x0 PSE controller. The PD692x0 support up to
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12 PSE managers which can expose up to 96 physical ports. All
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physical ports available on a manager have to be described in the
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incremental order even if they are not used.
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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required:
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- "#address-cells"
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- "#size-cells"
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patternProperties:
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"^manager@[0-9a-b]$":
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type: object
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additionalProperties: false
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description:
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PD69208T4/PD69204T4/PD69208M PSE manager exposing 4 or 8 physical
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ports.
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properties:
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reg:
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description:
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Incremental index of the PSE manager starting from 0, ranging
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from lowest to highest chip select, up to 11.
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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patternProperties:
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'^port@[0-7]$':
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type: object
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additionalProperties: false
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properties:
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reg:
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maxItems: 1
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required:
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- reg
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required:
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- reg
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- "#address-cells"
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- "#size-cells"
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required:
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- compatible
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- reg
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- pse-pis
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unevaluatedProperties: false
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examples:
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- |
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-pse@3c {
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compatible = "microchip,pd69200";
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reg = <0x3c>;
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managers {
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#address-cells = <1>;
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#size-cells = <0>;
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manager@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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phys0: port@0 {
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reg = <0>;
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};
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phys1: port@1 {
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reg = <1>;
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};
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phys2: port@2 {
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reg = <2>;
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};
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phys3: port@3 {
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reg = <3>;
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};
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};
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manager@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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phys4: port@0 {
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reg = <0>;
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};
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phys5: port@1 {
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reg = <1>;
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};
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phys6: port@2 {
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reg = <2>;
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};
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phys7: port@3 {
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reg = <3>;
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};
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};
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};
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pse-pis {
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#address-cells = <1>;
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#size-cells = <0>;
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pse_pi0: pse-pi@0 {
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reg = <0>;
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#pse-cells = <0>;
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pairset-names = "alternative-a", "alternative-b";
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pairsets = <&phys0>, <&phys1>;
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polarity-supported = "MDI", "S";
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vpwr-supply = <&vpwr1>;
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};
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pse_pi1: pse-pi@1 {
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reg = <1>;
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#pse-cells = <0>;
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pairset-names = "alternative-a";
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pairsets = <&phys2>;
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polarity-supported = "MDI";
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vpwr-supply = <&vpwr2>;
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};
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};
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};
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};
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