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Add a new driver, qat_6xxx, to support QAT GEN6 devices. QAT GEN6 devices are a follow-on generation of GEN4 devices and differently from the previous generation, they can support all three services (symmetric, asymmetric, and data compression) concurrently. In order to have the qat_6xxx driver to reuse some of the GEN4 logic, a new abstraction layer has been introduced to bridge the two implementations. This allows to avoid code duplication and to keep the qat_6xxx driver isolated from the GEN4 logic. This approach has been used for the PF to VF logic and the HW CSR access logic. Signed-off-by: Laurent M Coquerel <laurent.m.coquerel@intel.com> Co-developed-by: George Abraham P <george.abraham.p@intel.com> Signed-off-by: George Abraham P <george.abraham.p@intel.com> Co-developed-by: Karthikeyan Gopal <karthikeyan.gopal@intel.com> Signed-off-by: Karthikeyan Gopal <karthikeyan.gopal@intel.com> Co-developed-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com> Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
29 lines
696 B
C
29 lines
696 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2025 Intel Corporation */
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#ifndef ADF_GEN6_PM_H
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#define ADF_GEN6_PM_H
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#include <linux/bits.h>
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#include <linux/time.h>
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struct adf_accel_dev;
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/* Power management */
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#define ADF_GEN6_PM_POLL_DELAY_US 20
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#define ADF_GEN6_PM_POLL_TIMEOUT_US USEC_PER_SEC
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#define ADF_GEN6_PM_STATUS 0x50A00C
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#define ADF_GEN6_PM_INTERRUPT 0x50A028
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/* Power management source in ERRSOU2 and ERRMSK2 */
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#define ADF_GEN6_PM_SOU BIT(18)
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/* cpm_pm_interrupt bitfields */
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#define ADF_GEN6_PM_DRV_ACTIVE BIT(20)
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#define ADF_GEN6_PM_DEFAULT_IDLE_FILTER 0x6
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/* cpm_pm_status bitfields */
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#define ADF_GEN6_PM_INIT_STATE BIT(21)
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#endif /* ADF_GEN6_PM_H */
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