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From VOLTA_CHANNEL_GPFIFO_A onwards, HW no longer updates the GET/GP_GET pointers in USERD following channel progress, but instead updates on a timer for compatibility, and SW is expected to implement its own method of tracking channel progress (typically via non-WFI semaphore release). Nouveau has been making use of the compatibility mode up until now, however, from BLACKWELL_CHANNEL_GPFIFO_A HW no longer supports USERD writeback at all. Allocate a per-channel buffer in system memory, and append a non-WFI semaphore release to the end of each push buffer segment to simulate the pointers previously read from USERD. This change is implemented for Fermi (which is the first to support non- WFI semaphore release) onwards, as readback from system memory is likely faster than BAR1 reads. Signed-off-by: Ben Skeggs <bskeggs@nvidia.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Timur Tabi <ttabi@nvidia.com> Tested-by: Timur Tabi <ttabi@nvidia.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
94 lines
2.6 KiB
C
94 lines
2.6 KiB
C
/* SPDX-License-Identifier: MIT
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*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <nvif/chan.h>
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#include <nvif/user.h>
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#include <nvif/push906f.h>
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#include <nvhw/class/cl906f.h>
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/* Limits GPFIFO size to 1MiB, and "main" push buffer size to 64KiB. */
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#define NVIF_CHAN906F_PBPTR_BITS 15
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#define NVIF_CHAN906F_PBPTR_MASK ((1 << NVIF_CHAN906F_PBPTR_BITS) - 1)
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#define NVIF_CHAN906F_GPPTR_SHIFT NVIF_CHAN906F_PBPTR_BITS
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#define NVIF_CHAN906F_GPPTR_BITS (32 - NVIF_CHAN906F_PBPTR_BITS)
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#define NVIF_CHAN906F_GPPTR_MASK ((1 << NVIF_CHAN906F_GPPTR_BITS) - 1)
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#define NVIF_CHAN906F_SEM_RELEASE_SIZE 5
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static int
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nvif_chan906f_sem_release(struct nvif_chan *chan, u64 addr, u32 data)
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{
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struct nvif_push *push = &chan->push;
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int ret;
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ret = PUSH_WAIT(push, NVIF_CHAN906F_SEM_RELEASE_SIZE);
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if (ret)
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return ret;
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PUSH_MTHD(push, NV906F, SEMAPHOREA,
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NVVAL(NV906F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(addr)),
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SEMAPHOREB, lower_32_bits(addr),
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SEMAPHOREC, data,
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SEMAPHORED,
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NVDEF(NV906F, SEMAPHORED, OPERATION, RELEASE) |
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NVDEF(NV906F, SEMAPHORED, RELEASE_WFI, DIS) |
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NVDEF(NV906F, SEMAPHORED, RELEASE_SIZE, 16BYTE));
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return 0;
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}
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int
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nvif_chan906f_gpfifo_post(struct nvif_chan *chan, u32 gpptr, u32 pbptr)
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{
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return chan->func->sem.release(chan, chan->sema.addr,
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(gpptr << NVIF_CHAN906F_GPPTR_SHIFT) | pbptr);
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}
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u32
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nvif_chan906f_gpfifo_read_get(struct nvif_chan *chan)
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{
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return nvif_rd32(&chan->sema, 0) >> NVIF_CHAN906F_GPPTR_SHIFT;
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}
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u32
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nvif_chan906f_read_get(struct nvif_chan *chan)
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{
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return nvif_rd32(&chan->sema, 0) & NVIF_CHAN906F_PBPTR_MASK;
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}
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static const struct nvif_chan_func
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nvif_chan906f = {
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.push.read_get = nvif_chan906f_read_get,
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.gpfifo.read_get = nvif_chan906f_gpfifo_read_get,
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.gpfifo.push = nvif_chan506f_gpfifo_push,
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.gpfifo.kick = nvif_chan506f_gpfifo_kick,
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.gpfifo.post = nvif_chan906f_gpfifo_post,
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.gpfifo.post_size = NVIF_CHAN906F_SEM_RELEASE_SIZE,
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.sem.release = nvif_chan906f_sem_release,
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};
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int
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nvif_chan906f_ctor_(const struct nvif_chan_func *func, void *userd, void *gpfifo, u32 gpfifo_size,
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void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr,
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struct nvif_chan *chan)
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{
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nvif_chan_gpfifo_ctor(func, userd, gpfifo, gpfifo_size, push, push_addr, push_size, chan);
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chan->sema.map.ptr = sema;
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chan->sema.addr = sema_addr;
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return 0;
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}
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int
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nvif_chan906f_ctor(struct nvif_chan *chan, void *userd, void *gpfifo, u32 gpfifo_size,
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void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr)
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{
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return nvif_chan906f_ctor_(&nvif_chan906f, userd, gpfifo, gpfifo_size,
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push, push_addr, push_size, sema, sema_addr, chan);
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}
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