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5488bec96b
Allow user to provide a low latency hint. When set, KMD sends a hint
to GuC which results in special handling for that process. SLPC will
ramp the GT frequency aggressively every time it switches to this
process.
We need to enable the use of SLPC Compute strategy during init, but
it will apply only to processes that set this bit during process
creation.
Improvement with this approach as below:
Before,
:~$ NEOReadDebugKeys=1 EnableDirectSubmission=0 clpeak --kernel-latency
Platform: Intel(R) OpenCL Graphics
Device: Intel(R) Graphics [0xe20b]
Driver version : 24.52.0 (Linux x64)
Compute units : 160
Clock frequency : 2850 MHz
Kernel launch latency : 283.16 us
After,
:~$ NEOReadDebugKeys=1 EnableDirectSubmission=0 clpeak --kernel-latency
Platform: Intel(R) OpenCL Graphics
Device: Intel(R) Graphics [0xe20b]
Driver version : 24.52.0 (Linux x64)
Compute units : 160
Clock frequency : 2850 MHz
Kernel launch latency : 63.38 us
Compute PR: https://github.com/intel/compute-runtime/pull/794
Mesa PR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33214
IGT PR: https://patchwork.freedesktop.org/patch/639989/
V10(Lucas):
- Remove doc from drm-uapi.rst
v9(Vinay):
- remove extra line, align commit message
v8(Vinay):
- Add separate example for using low latency hint
v7(Jose):
- Update UMD PR
- applicable to all gpus
V6:
- init flags, remove redundant flags check (MAuld)
V5:
- Move uapi doc to documentation and GuC ABI specific change (Rodrigo)
- Modify logic to restrict exec queue flags (MAuld)
V4:
- To make it clear, dont use exec queue word (Vinay)
- Correct typo in description of flag (Jose/Vinay)
- rename set_strategy api and replace ctx with exec queue(Vinay)
- Start with 0th bit to indentify user flags (Jose)
V3:
- Conver user flag to kernel internal flag and use (Oak)
- Support query config for use to check kernel support (Jose)
- Dont need to take runtime pm (Vinay)
V2:
- DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT 1 planned for other hint(Szymon)
- Add motivation to description (Lucas)
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250228070224.739295-2-tejas.upadhyay@intel.com
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
275 lines
11 KiB
C
275 lines
11 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2021 Intel Corporation
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*/
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#ifndef _GUC_ACTIONS_SLPC_ABI_H_
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#define _GUC_ACTIONS_SLPC_ABI_H_
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#include <linux/types.h>
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/**
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* DOC: SLPC SHARED DATA STRUCTURE
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*
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* +----+------+--------------------------------------------------------------+
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* | CL | Bytes| Description |
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* +====+======+==============================================================+
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* | 1 | 0-3 | SHARED DATA SIZE |
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* | +------+--------------------------------------------------------------+
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* | | 4-7 | GLOBAL STATE |
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* | +------+--------------------------------------------------------------+
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* | | 8-11 | DISPLAY DATA ADDRESS |
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* | +------+--------------------------------------------------------------+
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* | | 12:63| PADDING |
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* +----+------+--------------------------------------------------------------+
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* | | 0:63 | PADDING(PLATFORM INFO) |
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* +----+------+--------------------------------------------------------------+
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* | 3 | 0-3 | TASK STATE DATA |
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* + +------+--------------------------------------------------------------+
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* | | 4:63 | PADDING |
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* +----+------+--------------------------------------------------------------+
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* |4-21|0:1087| OVERRIDE PARAMS AND BIT FIELDS |
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* +----+------+--------------------------------------------------------------+
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* | | | PADDING + EXTRA RESERVED PAGE |
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* +----+------+--------------------------------------------------------------+
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*/
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/*
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* SLPC exposes certain parameters for global configuration by the host.
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* These are referred to as override parameters, because in most cases
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* the host will not need to modify the default values used by SLPC.
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* SLPC remembers the default values which allows the host to easily restore
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* them by simply unsetting the override. The host can set or unset override
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* parameters during SLPC (re-)initialization using the SLPC Reset event.
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* The host can also set or unset override parameters on the fly using the
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* Parameter Set and Parameter Unset events
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*/
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#define SLPC_MAX_OVERRIDE_PARAMETERS 256
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#define SLPC_OVERRIDE_BITFIELD_SIZE \
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(SLPC_MAX_OVERRIDE_PARAMETERS / 32)
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#define SLPC_PAGE_SIZE_BYTES 4096
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#define SLPC_CACHELINE_SIZE_BYTES 64
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#define SLPC_SHARED_DATA_SIZE_BYTE_HEADER SLPC_CACHELINE_SIZE_BYTES
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#define SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO SLPC_CACHELINE_SIZE_BYTES
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#define SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE SLPC_CACHELINE_SIZE_BYTES
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#define SLPC_SHARED_DATA_MODE_DEFN_TABLE_SIZE SLPC_PAGE_SIZE_BYTES
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#define SLPC_SHARED_DATA_SIZE_BYTE_MAX (2 * SLPC_PAGE_SIZE_BYTES)
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/*
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* Cacheline size aligned (Total size needed for
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* SLPM_KMD_MAX_OVERRIDE_PARAMETERS=256 is 1088 bytes)
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*/
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#define SLPC_OVERRIDE_PARAMS_TOTAL_BYTES (((((SLPC_MAX_OVERRIDE_PARAMETERS * 4) \
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+ ((SLPC_MAX_OVERRIDE_PARAMETERS / 32) * 4)) \
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+ (SLPC_CACHELINE_SIZE_BYTES - 1)) / SLPC_CACHELINE_SIZE_BYTES) * \
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SLPC_CACHELINE_SIZE_BYTES)
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#define SLPC_SHARED_DATA_SIZE_BYTE_OTHER (SLPC_SHARED_DATA_SIZE_BYTE_MAX - \
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(SLPC_SHARED_DATA_SIZE_BYTE_HEADER \
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+ SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO \
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+ SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE \
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+ SLPC_OVERRIDE_PARAMS_TOTAL_BYTES \
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+ SLPC_SHARED_DATA_MODE_DEFN_TABLE_SIZE))
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enum slpc_task_enable {
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SLPC_PARAM_TASK_DEFAULT = 0,
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SLPC_PARAM_TASK_ENABLED,
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SLPC_PARAM_TASK_DISABLED,
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SLPC_PARAM_TASK_UNKNOWN
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};
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enum slpc_global_state {
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SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
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SLPC_GLOBAL_STATE_INITIALIZING = 1,
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SLPC_GLOBAL_STATE_RESETTING = 2,
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SLPC_GLOBAL_STATE_RUNNING = 3,
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SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
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SLPC_GLOBAL_STATE_ERROR = 5
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};
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enum slpc_param_id {
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SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
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SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
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SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
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SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
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SLPC_PARAM_TASK_ENABLE_DCC = 4,
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SLPC_PARAM_TASK_DISABLE_DCC = 5,
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SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
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SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
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SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
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SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
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SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
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SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
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SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
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SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
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SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
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SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
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SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
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SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,
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SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,
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SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,
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SLPC_PARAM_GLOBAL_RT_MODE_TURBO_FREQ_DELTA_MHZ = 20,
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SLPC_PARAM_PWRGATE_RC_MODE = 21,
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SLPC_PARAM_EDR_MODE_COMPUTE_TIMEOUT_MS = 22,
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SLPC_PARAM_EDR_QOS_FREQ_MHZ = 23,
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SLPC_PARAM_MEDIA_FF_RATIO_MODE = 24,
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SLPC_PARAM_ENABLE_IA_FREQ_LIMITING = 25,
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SLPC_PARAM_STRATEGIES = 26,
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SLPC_PARAM_POWER_PROFILE = 27,
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SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY = 28,
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SLPC_MAX_PARAM = 32,
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};
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enum slpc_media_ratio_mode {
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SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL = 0,
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SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE = 1,
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SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO = 2,
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};
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enum slpc_gucrc_mode {
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SLPC_GUCRC_MODE_HW = 0,
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SLPC_GUCRC_MODE_GUCRC_NO_RC6 = 1,
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SLPC_GUCRC_MODE_GUCRC_STATIC_TIMEOUT = 2,
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SLPC_GUCRC_MODE_GUCRC_DYNAMIC_HYSTERESIS = 3,
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SLPC_GUCRC_MODE_MAX,
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};
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enum slpc_event_id {
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SLPC_EVENT_RESET = 0,
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SLPC_EVENT_SHUTDOWN = 1,
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SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
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SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
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SLPC_EVENT_FLIP_COMPLETE = 4,
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SLPC_EVENT_QUERY_TASK_STATE = 5,
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SLPC_EVENT_PARAMETER_SET = 6,
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SLPC_EVENT_PARAMETER_UNSET = 7,
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};
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struct slpc_task_state_data {
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union {
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u32 task_status_padding;
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struct {
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u32 status;
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#define SLPC_GTPERF_TASK_ENABLED REG_BIT(0)
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#define SLPC_DCC_TASK_ENABLED REG_BIT(11)
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#define SLPC_IN_DCC REG_BIT(12)
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#define SLPC_BALANCER_ENABLED REG_BIT(15)
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#define SLPC_IBC_TASK_ENABLED REG_BIT(16)
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#define SLPC_BALANCER_IA_LMT_ENABLED REG_BIT(17)
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#define SLPC_BALANCER_IA_LMT_ACTIVE REG_BIT(18)
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};
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};
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union {
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u32 freq_padding;
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struct {
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#define SLPC_MAX_UNSLICE_FREQ_MASK REG_GENMASK(7, 0)
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#define SLPC_MIN_UNSLICE_FREQ_MASK REG_GENMASK(15, 8)
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#define SLPC_MAX_SLICE_FREQ_MASK REG_GENMASK(23, 16)
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#define SLPC_MIN_SLICE_FREQ_MASK REG_GENMASK(31, 24)
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u32 freq;
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};
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};
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} __packed;
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#define SLPC_CTX_FREQ_REQ_IS_COMPUTE REG_BIT(28)
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#define SLPC_OPTIMIZED_STRATEGY_COMPUTE REG_BIT(0)
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struct slpc_shared_data_header {
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/* Total size in bytes of this shared buffer. */
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u32 size;
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u32 global_state;
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u32 display_data_addr;
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} __packed;
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struct slpc_override_params {
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u32 bits[SLPC_OVERRIDE_BITFIELD_SIZE];
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u32 values[SLPC_MAX_OVERRIDE_PARAMETERS];
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} __packed;
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struct slpc_shared_data {
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struct slpc_shared_data_header header;
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u8 shared_data_header_pad[SLPC_SHARED_DATA_SIZE_BYTE_HEADER -
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sizeof(struct slpc_shared_data_header)];
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u8 platform_info_pad[SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO];
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struct slpc_task_state_data task_state_data;
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u8 task_state_data_pad[SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE -
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sizeof(struct slpc_task_state_data)];
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struct slpc_override_params override_params;
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u8 override_params_pad[SLPC_OVERRIDE_PARAMS_TOTAL_BYTES -
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sizeof(struct slpc_override_params)];
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u8 shared_data_pad[SLPC_SHARED_DATA_SIZE_BYTE_OTHER];
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/* PAGE 2 (4096 bytes), mode based parameter will be removed soon */
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u8 reserved_mode_definition[4096];
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} __packed;
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/**
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* DOC: SLPC H2G MESSAGE FORMAT
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*
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* +---+-------+--------------------------------------------------------------+
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* | | Bits | Description |
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* +===+=======+==============================================================+
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* | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_HOST_ |
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* | +-------+--------------------------------------------------------------+
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* | | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ |
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* | +-------+--------------------------------------------------------------+
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* | | 27:16 | DATA0 = MBZ |
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* | +-------+--------------------------------------------------------------+
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* | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_PC_SLPM_REQUEST` = 0x3003 |
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* +---+-------+--------------------------------------------------------------+
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* | 1 | 31:8 | **EVENT_ID** |
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* + +-------+--------------------------------------------------------------+
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* | | 7:0 | **EVENT_ARGC** - number of data arguments |
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* +---+-------+--------------------------------------------------------------+
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* | 2 | 31:0 | **EVENT_DATA1** |
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* +---+-------+--------------------------------------------------------------+
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* |...| 31:0 | ... |
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* +---+-------+--------------------------------------------------------------+
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* |2+n| 31:0 | **EVENT_DATAn** |
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* +---+-------+--------------------------------------------------------------+
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*/
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#define GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST 0x3003
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#define HOST2GUC_PC_SLPC_REQUEST_MSG_MIN_LEN \
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(GUC_HXG_REQUEST_MSG_MIN_LEN + 1u)
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#define HOST2GUC_PC_SLPC_EVENT_MAX_INPUT_ARGS 9
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#define HOST2GUC_PC_SLPC_REQUEST_MSG_MAX_LEN \
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(HOST2GUC_PC_SLPC_REQUEST_REQUEST_MSG_MIN_LEN + \
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HOST2GUC_PC_SLPC_EVENT_MAX_INPUT_ARGS)
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#define HOST2GUC_PC_SLPC_REQUEST_MSG_0_MBZ GUC_HXG_REQUEST_MSG_0_DATA0
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#define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID (0xffu << 8)
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#define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC (0xffu << 0)
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#define HOST2GUC_PC_SLPC_REQUEST_MSG_N_EVENT_DATA_N GUC_HXG_REQUEST_MSG_n_DATAn
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/**
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* DOC: SETUP_PC_GUCRC
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*
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* +---+-------+--------------------------------------------------------------+
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* | | Bits | Description |
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* +===+=======+==============================================================+
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* | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_HOST_ |
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* | +-------+--------------------------------------------------------------+
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* | | 30:28 | TYPE = GUC_HXG_TYPE_FAST_REQUEST_ |
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* | +-------+--------------------------------------------------------------+
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* | | 27:16 | DATA0 = MBZ |
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* | +-------+--------------------------------------------------------------+
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* | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC` = 0x3004 |
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* +---+-------+--------------------------------------------------------------+
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* | 1 | 31:0 | **MODE** = GUCRC_HOST_CONTROL(0), GUCRC_FIRMWARE_CONTROL(1) |
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* +---+-------+--------------------------------------------------------------+
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*/
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#define GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC 0x3004u
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#define GUCRC_HOST_CONTROL 0u
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#define GUCRC_FIRMWARE_CONTROL 1u
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#endif
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