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dd26402642
Upon detecting the ID for the ESMT F50D1G41LB chip, the fifth byte
returned is always 0x00 instead of the expected JEDEC continuation code
of 0x7f. This causes detection to fail:
[ 0.304399] spi-nand spi0.0: unknown raw ID c8117f7f00
[ 0.508943] spi-nand: probe of spi0.0 failed with error -524
So let's revert back to the 4 byte ID code for this chip
specifically.
Fixes: 4bd14b2fd8 ("mtd: spinand: esmt: Extend IDs to 5 bytes")
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
234 lines
7.8 KiB
C
234 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Author:
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* Chuanhong Guo <gch981213@gmail.com> - the main driver logic
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* Martin Kurbanov <mmkurbanov@sberdevices.ru> - OOB layout
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*/
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/mtd/spinand.h>
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#include <linux/spi/spi-mem.h>
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/* ESMT uses GigaDevice 0xc8 JECDEC ID on some SPI NANDs */
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#define SPINAND_MFR_ESMT_C8 0xc8
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#define ESMT_F50L1G41LB_CFG_OTP_PROTECT BIT(7)
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#define ESMT_F50L1G41LB_CFG_OTP_LOCK \
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(CFG_OTP_ENABLE | ESMT_F50L1G41LB_CFG_OTP_PROTECT)
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static SPINAND_OP_VARIANTS(read_cache_variants,
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SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0));
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static SPINAND_OP_VARIANTS(write_cache_variants,
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SPINAND_PROG_LOAD_1S_1S_4S_OP(true, 0, NULL, 0),
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SPINAND_PROG_LOAD_1S_1S_1S_OP(true, 0, NULL, 0));
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static SPINAND_OP_VARIANTS(update_cache_variants,
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SPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0),
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SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0));
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/*
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* OOB spare area map (64 bytes)
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*
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* Bad Block Markers
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* filled by HW and kernel Reserved
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* | +-----------------------+-----------------------+
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* | | | |
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* | | OOB free data Area |non ECC protected |
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* | +-------------|-----+-----------------|-----+-----------------|-----+
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* | | | | | | | |
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* +-|---|----------+--|-----|--------------+--|-----|--------------+--|-----|--------------+
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* | | | section0 | | | section1 | | | section2 | | | section3 |
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* +-v-+-v-+---+----+--v--+--v--+-----+-----+--v--+--v--+-----+-----+--v--+--v--+-----+-----+
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* | | | | | | | | | | | | | | | | |
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* |0:1|2:3|4:7|8:15|16:17|18:19|20:23|24:31|32:33|34:35|36:39|40:47|48:49|50:51|52:55|56:63|
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* | | | | | | | | | | | | | | | | |
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* +---+---+-^-+--^-+-----+-----+--^--+--^--+-----+-----+--^--+--^--+-----+-----+--^--+--^--+
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* | | | | | | | |
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* | +----------------|-----+-----------------|-----+-----------------|-----+
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* | ECC Area|(Main + Spare) - filled|by ESMT NAND HW |
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* | | | |
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* +---------------------+-----------------------+-----------------------+
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* OOB ECC protected Area - not used due to
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* partial programming from some filesystems
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* (like JFFS2 with cleanmarkers)
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*/
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#define ESMT_OOB_SECTION_COUNT 4
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#define ESMT_OOB_SECTION_SIZE(nand) \
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(nanddev_per_page_oobsize(nand) / ESMT_OOB_SECTION_COUNT)
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#define ESMT_OOB_FREE_SIZE(nand) \
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(ESMT_OOB_SECTION_SIZE(nand) / 2)
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#define ESMT_OOB_ECC_SIZE(nand) \
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(ESMT_OOB_SECTION_SIZE(nand) - ESMT_OOB_FREE_SIZE(nand))
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#define ESMT_OOB_BBM_SIZE 2
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static int f50l1g41lb_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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struct nand_device *nand = mtd_to_nanddev(mtd);
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if (section >= ESMT_OOB_SECTION_COUNT)
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return -ERANGE;
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region->offset = section * ESMT_OOB_SECTION_SIZE(nand) +
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ESMT_OOB_FREE_SIZE(nand);
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region->length = ESMT_OOB_ECC_SIZE(nand);
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return 0;
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}
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static int f50l1g41lb_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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struct nand_device *nand = mtd_to_nanddev(mtd);
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if (section >= ESMT_OOB_SECTION_COUNT)
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return -ERANGE;
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/*
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* Reserve space for bad blocks markers (section0) and
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* reserved bytes (sections 1-3)
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*/
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region->offset = section * ESMT_OOB_SECTION_SIZE(nand) + 2;
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/* Use only 2 non-protected ECC bytes per each OOB section */
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region->length = 2;
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return 0;
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}
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static const struct mtd_ooblayout_ops f50l1g41lb_ooblayout = {
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.ecc = f50l1g41lb_ooblayout_ecc,
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.free = f50l1g41lb_ooblayout_free,
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};
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static int f50l1g41lb_otp_info(struct spinand_device *spinand, size_t len,
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struct otp_info *buf, size_t *retlen, bool user)
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{
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if (len < sizeof(*buf))
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return -EINVAL;
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buf->locked = 0;
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buf->start = 0;
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buf->length = user ? spinand_user_otp_size(spinand) :
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spinand_fact_otp_size(spinand);
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*retlen = sizeof(*buf);
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return 0;
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}
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static int f50l1g41lb_fact_otp_info(struct spinand_device *spinand, size_t len,
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struct otp_info *buf, size_t *retlen)
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{
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return f50l1g41lb_otp_info(spinand, len, buf, retlen, false);
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}
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static int f50l1g41lb_user_otp_info(struct spinand_device *spinand, size_t len,
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struct otp_info *buf, size_t *retlen)
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{
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return f50l1g41lb_otp_info(spinand, len, buf, retlen, true);
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}
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static int f50l1g41lb_otp_lock(struct spinand_device *spinand, loff_t from,
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size_t len)
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{
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struct spi_mem_op write_op = SPINAND_WR_EN_DIS_1S_0_0_OP(true);
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struct spi_mem_op exec_op = SPINAND_PROG_EXEC_1S_1S_0_OP(0);
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u8 status;
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int ret;
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ret = spinand_upd_cfg(spinand, ESMT_F50L1G41LB_CFG_OTP_LOCK,
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ESMT_F50L1G41LB_CFG_OTP_LOCK);
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if (!ret)
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return ret;
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ret = spi_mem_exec_op(spinand->spimem, &write_op);
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if (!ret)
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goto out;
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ret = spi_mem_exec_op(spinand->spimem, &exec_op);
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if (!ret)
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goto out;
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ret = spinand_wait(spinand,
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SPINAND_WRITE_INITIAL_DELAY_US,
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SPINAND_WRITE_POLL_DELAY_US,
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&status);
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if (!ret && (status & STATUS_PROG_FAILED))
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ret = -EIO;
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out:
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if (spinand_upd_cfg(spinand, ESMT_F50L1G41LB_CFG_OTP_LOCK, 0)) {
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dev_warn(&spinand_to_mtd(spinand)->dev,
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"Can not disable OTP mode\n");
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ret = -EIO;
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}
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return ret;
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}
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static const struct spinand_user_otp_ops f50l1g41lb_user_otp_ops = {
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.info = f50l1g41lb_user_otp_info,
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.lock = f50l1g41lb_otp_lock,
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.read = spinand_user_otp_read,
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.write = spinand_user_otp_write,
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};
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static const struct spinand_fact_otp_ops f50l1g41lb_fact_otp_ops = {
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.info = f50l1g41lb_fact_otp_info,
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.read = spinand_fact_otp_read,
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};
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static const struct spinand_info esmt_c8_spinand_table[] = {
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SPINAND_INFO("F50L1G41LB",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01, 0x7f,
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0x7f, 0x7f),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(1, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL),
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SPINAND_USER_OTP_INFO(28, 2, &f50l1g41lb_user_otp_ops),
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SPINAND_FACT_OTP_INFO(2, 0, &f50l1g41lb_fact_otp_ops)),
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SPINAND_INFO("F50D1G41LB",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x11, 0x7f,
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0x7f),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(1, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL),
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SPINAND_USER_OTP_INFO(28, 2, &f50l1g41lb_user_otp_ops),
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SPINAND_FACT_OTP_INFO(2, 0, &f50l1g41lb_fact_otp_ops)),
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SPINAND_INFO("F50D2G41KA",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x51, 0x7f,
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0x7f, 0x7f),
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NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)),
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};
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static const struct spinand_manufacturer_ops esmt_spinand_manuf_ops = {
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};
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const struct spinand_manufacturer esmt_c8_spinand_manufacturer = {
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.id = SPINAND_MFR_ESMT_C8,
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.name = "ESMT",
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.chips = esmt_c8_spinand_table,
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.nchips = ARRAY_SIZE(esmt_c8_spinand_table),
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.ops = &esmt_spinand_manuf_ops,
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};
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