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https://github.com/torvalds/linux.git
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Pull drm updates from Dave Airlie:
"Highlights:
- Intel xe enable Panthor Lake, started adding WildCat Lake
- amdgpu has a bunch of reset improvments along with the usual IP
updates
- msm got VM_BIND support which is important for vulkan sparse memory
- more drm_panic users
- gpusvm common code to handle a bunch of core SVM work outside
drivers.
Detail summary:
Changes outside drm subdirectory:
- 'shrink_shmem_memory()' for better shmem/hibernate interaction
- Rust support infrastructure:
- make ETIMEDOUT available
- add size constants up to SZ_2G
- add DMA coherent allocation bindings
- mtd driver for Intel GPU non-volatile storage
- i2c designware quirk for Intel xe
core:
- atomic helpers: tune enable/disable sequences
- add task info to wedge API
- refactor EDID quirks
- connector: move HDR sink to drm_display_info
- fourcc: half-float and 32-bit float formats
- mode_config: pass format info to simplify
dma-buf:
- heaps: Give CMA heap a stable name
ci:
- add device tree validation and kunit
displayport:
- change AUX DPCD access probe address
- add quirk for DPCD probe
- add panel replay definitions
- backlight control helpers
fbdev:
- make CONFIG_FIRMWARE_EDID available on all arches
fence:
- fix UAF issues
format-helper:
- improve tests
gpusvm:
- introduce devmem only flag for allocation
- add timeslicing support to GPU SVM
ttm:
- improve eviction
sched:
- tracing improvements
- kunit improvements
- memory leak fixes
- reset handling improvements
color mgmt:
- add hardware gamma LUT handling helpers
bridge:
- add destroy hook
- switch to reference counted drm_bridge allocations
- tc358767: convert to devm_drm_bridge_alloc
- improve CEC handling
panel:
- switch to reference counter drm_panel allocations
- fwnode panel lookup
- Huiling hl055fhv028c support
- Raspberry Pi 7" 720x1280 support
- edp: KDC KD116N3730A05, N160JCE-ELL CMN, N116BCJ-EAK
- simple: AUO P238HAN01
- st7701: Winstar wf40eswaa6mnn0
- visionox: rm69299-shift
- Renesas R61307, Renesas R69328 support
- DJN HX83112B
hdmi:
- add CEC handling
- YUV420 output support
xe:
- WildCat Lake support
- Enable PanthorLake by default
- mark BMG as SRIOV capable
- update firmware recommendations
- Expose media OA units
- aux-bux support for non-volatile memory
- MTD intel-dg driver for non-volatile memory
- Expose fan control and voltage regulator in sysfs
- restructure migration for multi-device
- Restore GuC submit UAF fix
- make GEM shrinker drm managed
- SRIOV VF Post-migration recovery of GGTT nodes
- W/A additions/reworks
- Prefetch support for svm ranges
- Don't allocate managed BO for each policy change
- HWMON fixes for BMG
- Create LRC BO without VM
- PCI ID updates
- make SLPC debugfs files optional
- rework eviction rejection of bound external BOs
- consolidate PAT programming logic for pre/post Xe2
- init changes for flicker-free boot
- Enable GuC Dynamic Inhibit Context switch
i915:
- drm_panic support for i915/xe
- initial flip queue off by default for LNL/PNL
- Wildcat Lake Display support
- Support for DSC fractional link bpp
- Support for simultaneous Panel Replay and Adaptive sync
- Support for PTL+ double buffer LUT
- initial PIPEDMC event handling
- drm_panel_follower support
- DPLL interface renames
- allocate struct intel_display dynamically
- flip queue preperation
- abstract DRAM detection better
- avoid GuC scheduling stalls
- remove DG1 force probe requirement
- fix MEI interrupt handler on RT kernels
- use backlight control helpers for eDP
- more shared display code refactoring
amdgpu:
- add userq slot to INFO ioctl
- SR-IOV hibernation support
- Suspend improvements
- Backlight improvements
- Use scaling for non-native eDP modes
- cleaner shader updates for GC 9.x
- Remove fence slab
- SDMA fw checks for userq support
- RAS updates
- DMCUB updates
- DP tunneling fixes
- Display idle D3 support
- Per queue reset improvements
- initial smartmux support
amdkfd:
- enable KFD on loongarch
- mtype fix for ext coherent system memory
radeon:
- CS validation additional GL extensions
- drop console lock during suspend/resume
- bump driver version
msm:
- VM BIND support
- CI: infrastructure updates
- UBWC single source of truth
- decouple GPU and KMS support
- DP: rework I/O accessors
- DPU: SM8750 support
- DSI: SM8750 support
- GPU: X1-45 support and speedbin support for X1-85
- MDSS: SM8750 support
nova:
- register! macro improvements
- DMA object abstraction
- VBIOS parser + fwsec lookup
- sysmem flush page support
- falcon: generic falcon boot code and HAL
- FWSEC-FRTS: fb setup and load/execute
ivpu:
- Add Wildcat Lake support
- Add turbo flag
ast:
- improve hardware generations implementation
imx:
- IMX8qxq Display Controller support
lima:
- Rockchip RK3528 GPU support
nouveau:
- fence handling cleanup
panfrost:
- MT8370 support
- bo labeling
- 64-bit register access
qaic:
- add RAS support
rockchip:
- convert inno_hdmi to a bridge
rz-du:
- add RZ/V2H(P) support
- MIPI-DSI DCS support
sitronix:
- ST7567 support
sun4i:
- add H616 support
tidss:
- add TI AM62L support
- AM65x OLDI bridge support
bochs:
- drm panic support
vkms:
- YUV and R* format support
- use faux device
vmwgfx:
- fence improvements
hyperv:
- move out of simple
- add drm_panic support"
* tag 'drm-next-2025-07-30' of https://gitlab.freedesktop.org/drm/kernel: (1479 commits)
drm/tidss: oldi: convert to devm_drm_bridge_alloc() API
drm/tidss: encoder: convert to devm_drm_bridge_alloc()
drm/amdgpu: move reset support type checks into the caller
drm/amdgpu/sdma7: re-emit unprocessed state on ring reset
drm/amdgpu/sdma6: re-emit unprocessed state on ring reset
drm/amdgpu/sdma5.2: re-emit unprocessed state on ring reset
drm/amdgpu/sdma5: re-emit unprocessed state on ring reset
drm/amdgpu/gfx12: re-emit unprocessed state on ring reset
drm/amdgpu/gfx11: re-emit unprocessed state on ring reset
drm/amdgpu/gfx10: re-emit unprocessed state on ring reset
drm/amdgpu/gfx9.4.3: re-emit unprocessed state on kcq reset
drm/amdgpu/gfx9: re-emit unprocessed state on kcq reset
drm/amdgpu: Add WARN_ON to the resource clear function
drm/amd/pm: Use cached metrics data on SMUv13.0.6
drm/amd/pm: Use cached data for min/max clocks
gpu: nova-core: fix bounds check in PmuLookupTableEntry::new
drm/amdgpu: Replace HQD terminology with slots naming
drm/amdgpu: Add user queue instance count in HW IP info
drm/amd/amdgpu: Add helper functions for isp buffers
drm/amd/amdgpu: Initialize swnode for ISP MFD device
...
128 lines
3.5 KiB
C
128 lines
3.5 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef _XE_GT_H_
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#define _XE_GT_H_
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#include <linux/fault-inject.h>
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#include <drm/drm_util.h>
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#include "xe_device.h"
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#include "xe_device_types.h"
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#include "xe_hw_engine.h"
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#define for_each_hw_engine(hwe__, gt__, id__) \
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for ((id__) = 0; (id__) < ARRAY_SIZE((gt__)->hw_engines); (id__)++) \
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for_each_if(((hwe__) = (gt__)->hw_engines + (id__)) && \
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xe_hw_engine_is_valid((hwe__)))
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#define CCS_MASK(gt) (((gt)->info.engine_mask & XE_HW_ENGINE_CCS_MASK) >> XE_HW_ENGINE_CCS0)
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extern struct fault_attr gt_reset_failure;
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static inline bool xe_fault_inject_gt_reset(void)
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{
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return IS_ENABLED(CONFIG_DEBUG_FS) && should_fail(>_reset_failure, 1);
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}
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struct xe_gt *xe_gt_alloc(struct xe_tile *tile);
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int xe_gt_init_early(struct xe_gt *gt);
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int xe_gt_init(struct xe_gt *gt);
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void xe_gt_mmio_init(struct xe_gt *gt);
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void xe_gt_declare_wedged(struct xe_gt *gt);
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int xe_gt_record_default_lrcs(struct xe_gt *gt);
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/**
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* xe_gt_record_user_engines - save data related to engines available to
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* userspace
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* @gt: GT structure
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*
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* Walk the available HW engines from gt->info.engine_mask and calculate data
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* related to those engines that may be used by userspace. To be used whenever
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* available engines change in runtime (e.g. with ccs_mode) or during
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* initialization
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*/
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void xe_gt_record_user_engines(struct xe_gt *gt);
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void xe_gt_suspend_prepare(struct xe_gt *gt);
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int xe_gt_suspend(struct xe_gt *gt);
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void xe_gt_shutdown(struct xe_gt *gt);
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int xe_gt_resume(struct xe_gt *gt);
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void xe_gt_reset_async(struct xe_gt *gt);
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void xe_gt_sanitize(struct xe_gt *gt);
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int xe_gt_sanitize_freq(struct xe_gt *gt);
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/**
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* xe_gt_wait_for_reset - wait for gt's async reset to finalize.
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* @gt: GT structure
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* Return:
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* %true if it waited for the work to finish execution,
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* %false if there was no scheduled reset or it was done.
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*/
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static inline bool xe_gt_wait_for_reset(struct xe_gt *gt)
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{
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return flush_work(>->reset.worker);
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}
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/**
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* xe_gt_reset - perform synchronous reset
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* @gt: GT structure
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* Return:
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* %true if it waited for the reset to finish,
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* %false if there was no scheduled reset.
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*/
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static inline bool xe_gt_reset(struct xe_gt *gt)
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{
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xe_gt_reset_async(gt);
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return xe_gt_wait_for_reset(gt);
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}
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/**
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* xe_gt_any_hw_engine_by_reset_domain - scan the list of engines and return the
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* first that matches the same reset domain as @class
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* @gt: GT structure
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* @class: hw engine class to lookup
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*/
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struct xe_hw_engine *
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xe_gt_any_hw_engine_by_reset_domain(struct xe_gt *gt, enum xe_engine_class class);
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/**
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* xe_gt_any_hw_engine - scan the list of engines and return the
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* first available
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* @gt: GT structure
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*/
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struct xe_hw_engine *xe_gt_any_hw_engine(struct xe_gt *gt);
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struct xe_hw_engine *xe_gt_hw_engine(struct xe_gt *gt,
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enum xe_engine_class class,
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u16 instance,
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bool logical);
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static inline bool xe_gt_has_indirect_ring_state(struct xe_gt *gt)
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{
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return gt->info.has_indirect_ring_state &&
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xe_device_uc_enabled(gt_to_xe(gt));
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}
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static inline bool xe_gt_is_main_type(struct xe_gt *gt)
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{
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return gt->info.type == XE_GT_TYPE_MAIN;
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}
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static inline bool xe_gt_is_media_type(struct xe_gt *gt)
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{
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return gt->info.type == XE_GT_TYPE_MEDIA;
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}
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static inline bool xe_gt_is_usm_hwe(struct xe_gt *gt, struct xe_hw_engine *hwe)
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{
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struct xe_device *xe = gt_to_xe(gt);
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return xe->info.has_usm && hwe->class == XE_ENGINE_CLASS_COPY &&
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hwe->instance == gt->usm.reserved_bcs_instance;
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}
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#endif
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