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4073e42028
Current port description doesn't cover all possible cases. It currently
expects one single port with two endpoints.
When the HDMI connector is described in the device tree there can be two
ports, first one going to the VOP and the second one going to the connector.
Also on SoCs which only have a single VOP there will be only one
endpoint instead of two.
This patch addresses both issues. With this there can either be a single
port ("port") , or two of them ("port@0", "port@1") when the connector
is also in the device tree. Also the first or only port can either have
one endpoint ("endpoint") for single VOP SoCs or two ("endpoint@0",
"endpoint@1") for dual VOP SoCs.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-25-s.hauer@pengutronix.de
167 lines
4.2 KiB
YAML
167 lines
4.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip DWC HDMI TX Encoder
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maintainers:
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- Mark Yao <markyao0591@gmail.com>
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description: |
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The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
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with a companion PHY IP.
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allOf:
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- $ref: ../bridge/synopsys,dw-hdmi.yaml#
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properties:
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compatible:
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enum:
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- rockchip,rk3228-dw-hdmi
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- rockchip,rk3288-dw-hdmi
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- rockchip,rk3328-dw-hdmi
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- rockchip,rk3399-dw-hdmi
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- rockchip,rk3568-dw-hdmi
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reg-io-width:
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const: 4
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avdd-0v9-supply:
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description:
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A 0.9V supply that powers up the SoC internal circuitry. The actual pin name
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varies between the different SoCs and is usually HDMI_TX_AVDD_0V9 or sometimes
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HDMI_AVDD_1V0.
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avdd-1v8-supply:
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description:
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A 1.8V supply that powers up the SoC internal circuitry. The pin name on the
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SoC usually is HDMI_TX_AVDD_1V8.
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clocks:
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minItems: 2
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items:
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- {}
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- {}
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# The next three clocks are all optional, but shall be specified in this
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# order when present.
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- description: The HDMI CEC controller main clock
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- description: Power for GRF IO
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- description: External clock for some HDMI PHY (old clock name, deprecated)
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- description: External clock for some HDMI PHY (new name)
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clock-names:
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minItems: 2
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items:
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- {}
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- {}
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- enum:
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- cec
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- grf
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- vpll
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- ref
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- enum:
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- grf
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- vpll
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- ref
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- enum:
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- vpll
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- ref
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ddc-i2c-bus:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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The HDMI DDC bus can be connected to either a system I2C master or the
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functionally-reduced I2C master contained in the DWC HDMI. When connected
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to a system I2C master this property contains a phandle to that I2C
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master controller.
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phys:
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maxItems: 1
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description: The HDMI PHY
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phy-names:
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const: hdmi
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pinctrl-names:
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description:
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The unwedge pinctrl entry shall drive the DDC SDA line low. This is
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intended to work around a hardware errata that can cause the DDC I2C
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bus to be wedged.
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minItems: 1
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items:
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- const: default
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- const: unwedge
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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patternProperties:
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"^port(@0)?$":
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$ref: /schemas/graph.yaml#/properties/port
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description: Input of the DWC HDMI TX
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properties:
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endpoint:
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description: Connection to the VOP
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endpoint@0:
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description: Connection to the VOPB
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endpoint@1:
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description: Connection to the VOPL
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properties:
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: Output of the DWC HDMI TX
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rockchip,grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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phandle to the GRF to mux vopl/vopb.
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required:
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- compatible
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- reg
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- reg-io-width
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- clocks
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- clock-names
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- interrupts
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- ports
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- rockchip,grf
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rk3288-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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hdmi: hdmi@ff980000 {
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compatible = "rockchip,rk3288-dw-hdmi";
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reg = <0xff980000 0x20000>;
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reg-io-width = <4>;
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ddc-i2c-bus = <&i2c5>;
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rockchip,grf = <&grf>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
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clock-names = "iahb", "isfr";
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ports {
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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hdmi_in_vopb: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vopb_out_hdmi>;
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};
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hdmi_in_vopl: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vopl_out_hdmi>;
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};
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};
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};
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};
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...
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