mirror of
https://github.com/torvalds/linux.git
synced 2026-04-19 07:13:56 -04:00
0e72db7767
Pull ARM devicetree updates from Arnd Bergmann:
"These are the devicetree updates for Arm and RISC-V based SoCs, mainly
from Qualcomm, NXP/Freescale, Aspeed, TI, Rockchips, Samsung, ST and
Starfive.
Only a few new SoC got added:
- TI AM62P5, a variant of the existing Sitara AM62x family
- Intel Agilex5, an FPGFA platform that includes an Cortex-A76/A55
SoC.
- Qualcomm ipq5018 is used in wireless access points
- Qualcomm SM4450 (Snapdragon 4 Gen 2) is a new low-end mobile phone
platform.
In total, 29 machines get added, which is low because of the summer
break. These cover SoCs from Aspeed, Broadcom, NXP, Samsung, ST,
Allwinner, Amlogic, Intel, Qualcomm, Rockchip, TI and T-Head. Most of
these are development and reference boards.
Despite not adding a lot of new machines, there are over 700 patches
in total, most of which are cleanups and minor fixes"
* tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (735 commits)
arm64: dts: use capital "OR" for multiple licenses in SPDX
ARM: dts: use capital "OR" for multiple licenses in SPDX
arm64: dts: qcom: sdm845-db845c: Mark cont splash memory region as reserved
ARM: dts: qcom: apq8064: add support to gsbi4 uart
riscv: dts: change TH1520 files to dual license
riscv: dts: thead: add BeagleV Ahead board device tree
dt-bindings: riscv: Add BeagleV Ahead board compatibles
ARM: dts: stm32: add SCMI PMIC regulators on stm32mp135f-dk board
ARM: dts: stm32: STM32MP13x SoC exposes SCMI regulators
dt-bindings: rcc: stm32: add STM32MP13 SCMI regulators IDs
ARM: dts: stm32: support display on stm32f746-disco board
ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f746-disco
ARM: dts: stm32: add pin map for LTDC on stm32f7
ARM: dts: stm32: add ltdc support on stm32f746 MCU
arm64: dts: qcom: sm6350: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sdm670: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sa8775p: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sc8280xp: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sdm670: Add PDC
riscv: dts: starfive: fix jh7110 qspi sort order
...
169 lines
4.5 KiB
YAML
169 lines
4.5 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/can/bosch,m_can.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Bosch MCAN controller
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description: Bosch MCAN controller for CAN bus
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maintainers:
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- Chandrasekar Ramakrishnan <rcsekar@samsung.com>
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allOf:
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- $ref: can-controller.yaml#
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properties:
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compatible:
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const: bosch,m_can
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reg:
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items:
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- description: M_CAN registers map
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- description: message RAM
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reg-names:
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items:
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- const: m_can
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- const: message_ram
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interrupts:
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items:
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- description: interrupt line0
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- description: interrupt line1
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minItems: 1
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interrupt-names:
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items:
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- const: int0
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- const: int1
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minItems: 1
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clocks:
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items:
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- description: peripheral clock
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- description: bus clock
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clock-names:
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items:
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- const: hclk
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- const: cclk
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bosch,mram-cfg:
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description: |
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Message RAM configuration data.
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Multiple M_CAN instances can share the same Message RAM
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and each element(e.g Rx FIFO or Tx Buffer and etc) number
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in Message RAM is also configurable, so this property is
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telling driver how the shared or private Message RAM are
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used by this M_CAN controller.
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The format should be as follows:
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<offset sidf_elems xidf_elems rxf0_elems rxf1_elems rxb_elems txe_elems txb_elems>
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The 'offset' is an address offset of the Message RAM where
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the following elements start from. This is usually set to
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0x0 if you're using a private Message RAM. The remain cells
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are used to specify how many elements are used for each FIFO/Buffer.
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M_CAN includes the following elements according to user manual:
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11-bit Filter 0-128 elements / 0-128 words
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29-bit Filter 0-64 elements / 0-128 words
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Rx FIFO 0 0-64 elements / 0-1152 words
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Rx FIFO 1 0-64 elements / 0-1152 words
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Rx Buffers 0-64 elements / 0-1152 words
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Tx Event FIFO 0-32 elements / 0-64 words
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Tx Buffers 0-32 elements / 0-576 words
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Please refer to 2.4.1 Message RAM Configuration in Bosch
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M_CAN user manual for details.
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$ref: /schemas/types.yaml#/definitions/int32-array
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items:
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- description: The 'offset' is an address offset of the Message RAM where
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the following elements start from. This is usually set to 0x0 if
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you're using a private Message RAM.
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default: 0
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- description: 11-bit Filter 0-128 elements / 0-128 words
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minimum: 0
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maximum: 128
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- description: 29-bit Filter 0-64 elements / 0-128 words
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minimum: 0
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maximum: 64
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- description: Rx FIFO 0 0-64 elements / 0-1152 words
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minimum: 0
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maximum: 64
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- description: Rx FIFO 1 0-64 elements / 0-1152 words
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minimum: 0
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maximum: 64
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- description: Rx Buffers 0-64 elements / 0-1152 words
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minimum: 0
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maximum: 64
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- description: Tx Event FIFO 0-32 elements / 0-64 words
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minimum: 0
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maximum: 32
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- description: Tx Buffers 0-32 elements / 0-576 words
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minimum: 0
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maximum: 32
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minItems: 1
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power-domains:
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description:
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Power domain provider node and an args specifier containing
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the can device id value.
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maxItems: 1
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can-transceiver:
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$ref: can-transceiver.yaml#
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phys:
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maxItems: 1
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- bosch,mram-cfg
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unevaluatedProperties: false
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examples:
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- |
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// Example with interrupts
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#include <dt-bindings/clock/imx6sx-clock.h>
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can@20e8000 {
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compatible = "bosch,m_can";
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reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
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reg-names = "m_can", "message_ram";
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interrupts = <0 114 0x04>, <0 114 0x04>;
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interrupt-names = "int0", "int1";
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clocks = <&clks IMX6SX_CLK_CANFD>,
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<&clks IMX6SX_CLK_CANFD>;
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clock-names = "hclk", "cclk";
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bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
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can-transceiver {
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max-bitrate = <5000000>;
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};
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};
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- |
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// Example with timer polling
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#include <dt-bindings/clock/imx6sx-clock.h>
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can@20e8000 {
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compatible = "bosch,m_can";
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reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
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reg-names = "m_can", "message_ram";
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clocks = <&clks IMX6SX_CLK_CANFD>,
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<&clks IMX6SX_CLK_CANFD>;
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clock-names = "hclk", "cclk";
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bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
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can-transceiver {
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max-bitrate = <5000000>;
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};
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};
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...
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