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Just as unevaluatedProperties or additionalProperties are required at the top level of schemas, they should (and will) also be required for child node schemas. That ensures only documented properties are present for any node. Add unevaluatedProperties or additionalProperties as appropriate. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Arınç ÜNAL <arinc.unal@arinc9.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Gerhard Engleder <gerhard@engleder-embedded.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20231016-dt-net-cleanups-v1-1-a525a090b444@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
389 lines
13 KiB
YAML
389 lines
13 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/dsa/realtek.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Realtek switches for unmanaged switches
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allOf:
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- $ref: dsa.yaml#/$defs/ethernet-ports
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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description:
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Realtek advertises these chips as fast/gigabit switches or unmanaged
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switches. They can be controlled using different interfaces, like SMI,
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MDIO or SPI.
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The SMI "Simple Management Interface" is a two-wire protocol using
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bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
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not use the MDIO protocol. This binding defines how to specify the
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SMI-based Realtek devices. The realtek-smi driver is a platform driver
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and it must be inserted inside a platform node.
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The MDIO-connected switches use MDIO protocol to access their registers.
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The realtek-mdio driver is an MDIO driver and it must be inserted inside
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an MDIO node.
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The compatible string is only used to identify which (silicon) family the
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switch belongs to. Roughly speaking, a family is any set of Realtek switches
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whose chip identification register(s) have a common location and semantics.
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The different models in a given family can be automatically disambiguated by
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parsing the chip identification register(s) according to the given family,
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avoiding the need for a unique compatible string for each model.
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properties:
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compatible:
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enum:
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- realtek,rtl8365mb
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- realtek,rtl8366rb
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description: |
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realtek,rtl8365mb:
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Use with models RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB,
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RTL8364NB, RTL8364NB-VB, RTL8365MB, RTL8366SC, RTL8367RB-VB, RTL8367S,
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RTL8367SB, RTL8370MB, RTL8310SR
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realtek,rtl8366rb:
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Use with models RTL8366RB, RTL8366S
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mdc-gpios:
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description: GPIO line for the MDC clock line.
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maxItems: 1
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mdio-gpios:
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description: GPIO line for the MDIO data line.
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maxItems: 1
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reset-gpios:
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description: GPIO to be used to reset the whole device
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maxItems: 1
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realtek,disable-leds:
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type: boolean
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description: |
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if the LED drivers are not used in the hardware design,
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this will disable them so they are not turned on
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and wasting power.
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interrupt-controller:
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type: object
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additionalProperties: false
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description: |
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This defines an interrupt controller with an IRQ line (typically
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a GPIO) that will demultiplex and handle the interrupt from the single
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interrupt line coming out of one of the Realtek switch chips. It most
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importantly provides link up/down interrupts to the PHY blocks inside
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the ASIC.
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properties:
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interrupt-controller: true
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interrupts:
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maxItems: 1
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description:
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A single IRQ line from the switch, either active LOW or HIGH
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'#address-cells':
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const: 0
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'#interrupt-cells':
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const: 1
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required:
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- interrupt-controller
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- '#address-cells'
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- '#interrupt-cells'
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mdio:
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$ref: /schemas/net/mdio.yaml#
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unevaluatedProperties: false
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properties:
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compatible:
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const: realtek,smi-mdio
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if:
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required:
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- reg
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then:
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$ref: /schemas/spi/spi-peripheral-props.yaml#
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not:
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required:
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- mdc-gpios
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- mdio-gpios
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- mdio
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properties:
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mdc-gpios: false
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mdio-gpios: false
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mdio: false
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else:
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required:
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- mdc-gpios
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- mdio-gpios
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- mdio
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- reset-gpios
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required:
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- compatible
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# - mdc-gpios
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# - mdio-gpios
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# - reset-gpios
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# - mdio
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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platform {
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switch {
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compatible = "realtek,rtl8366rb";
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/* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
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mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
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mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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switch_intc1: interrupt-controller {
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/* GPIO 15 provides the interrupt */
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interrupt-parent = <&gpio0>;
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interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan0";
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phy-handle = <&phy0>;
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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phy-handle = <&phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-handle = <&phy2>;
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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phy-handle = <&phy3>;
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};
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port@4 {
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reg = <4>;
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label = "wan";
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phy-handle = <&phy4>;
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};
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port@5 {
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reg = <5>;
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ethernet = <&gmac0>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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mdio {
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compatible = "realtek,smi-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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interrupt-parent = <&switch_intc1>;
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interrupts = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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interrupt-parent = <&switch_intc1>;
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interrupts = <1>;
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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interrupt-parent = <&switch_intc1>;
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interrupts = <2>;
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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interrupt-parent = <&switch_intc1>;
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interrupts = <3>;
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};
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phy4: ethernet-phy@4 {
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reg = <4>;
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interrupt-parent = <&switch_intc1>;
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interrupts = <12>;
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};
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};
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};
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};
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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platform {
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switch {
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compatible = "realtek,rtl8365mb";
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mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
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mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
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switch_intc2: interrupt-controller {
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interrupt-parent = <&gpio5>;
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interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "swp0";
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phy-handle = <ðphy0>;
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};
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port@1 {
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reg = <1>;
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label = "swp1";
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phy-handle = <ðphy1>;
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};
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port@2 {
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reg = <2>;
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label = "swp2";
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phy-handle = <ðphy2>;
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};
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port@3 {
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reg = <3>;
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label = "swp3";
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phy-handle = <ðphy3>;
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};
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port@6 {
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reg = <6>;
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ethernet = <&fec1>;
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phy-mode = "rgmii";
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tx-internal-delay-ps = <2000>;
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rx-internal-delay-ps = <2000>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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mdio {
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compatible = "realtek,smi-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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interrupt-parent = <&switch_intc2>;
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interrupts = <0>;
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};
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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interrupt-parent = <&switch_intc2>;
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interrupts = <1>;
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};
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ethphy2: ethernet-phy@2 {
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reg = <2>;
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interrupt-parent = <&switch_intc2>;
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interrupts = <2>;
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};
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ethphy3: ethernet-phy@3 {
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reg = <3>;
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interrupt-parent = <&switch_intc2>;
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interrupts = <3>;
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};
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};
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};
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};
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch@29 {
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compatible = "realtek,rtl8365mb";
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reg = <29>;
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reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
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switch_intc3: interrupt-controller {
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interrupt-parent = <&gpio0>;
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interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan4";
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};
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port@1 {
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reg = <1>;
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label = "lan3";
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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};
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port@3 {
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reg = <3>;
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label = "lan1";
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};
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port@4 {
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reg = <4>;
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label = "wan";
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};
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port@7 {
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reg = <7>;
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ethernet = <ðernet>;
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phy-mode = "rgmii";
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tx-internal-delay-ps = <2000>;
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rx-internal-delay-ps = <0>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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};
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