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Add support for Clocking Wizard for Versal adaptive compute acceleration platforms. The Versal clocking wizard differs in the programming model and the register layout. The CLKFBOUT_1 registers are at offset of 0x200 instead of the 0x330 in Versal. In Versal clocking wizard the low and high time is programmed instead of the divisor. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Link: https://lore.kernel.org/r/20231214105125.26919-3-shubhrajyoti.datta@amd.com [sboyd@kernel.org: Stop initializing spinlock flags] Signed-off-by: Stephen Boyd <sboyd@kernel.org>