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Xe2_LPD doesn't have south display engine on a PCH, it's actually on the SoC die (while north display engine is on compute die). As such it makes no sense to go through the PCI devices looking for an ISA bridge. The approach used by BXT/GLK can't be used here since leaving it with PCH_NONE would mean taking the wrong code paths. For the places we currently use a PCH check, it's enough for now to just check the north display version. Use that to define a fake PCH to be used across the driver. Eventually these PCH checks may need to be re-designed as this is already the third platform using/needing a fake PCH. v2: Match on display IP version rather than on platform (Matt Roper) v3: Extend and clarify commit message (Matt Roper / Ville) Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-6-lucas.demarchi@intel.com
94 lines
3.8 KiB
C
94 lines
3.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2019 Intel Corporation.
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*/
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#ifndef __INTEL_PCH__
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#define __INTEL_PCH__
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struct drm_i915_private;
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/*
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* Sorted by south display engine compatibility.
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* If the new PCH comes with a south display engine that is not
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* inherited from the latest item, please do not add it to the
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* end. Instead, add it right after its "parent" PCH.
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*/
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enum intel_pch {
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PCH_NOP = -1, /* PCH without south display */
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PCH_NONE = 0, /* No PCH present */
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PCH_IBX, /* Ibexpeak PCH */
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PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
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PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
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PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */
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PCH_CNP, /* Cannon/Comet Lake PCH */
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PCH_ICP, /* Ice Lake/Jasper Lake PCH */
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PCH_TGP, /* Tiger Lake/Mule Creek Canyon PCH */
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PCH_ADP, /* Alder Lake PCH */
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PCH_MTP, /* Meteor Lake PCH */
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/* Fake PCHs, functionality handled on the same PCI dev */
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PCH_DG1 = 1024,
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PCH_DG2,
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PCH_LNL,
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};
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#define INTEL_PCH_DEVICE_ID_MASK 0xff80
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#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
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#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
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#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
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#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
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#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
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#define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
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#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
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#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
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#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
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#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
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#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
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#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
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#define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
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#define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680
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#define INTEL_PCH_CMP_V_DEVICE_ID_TYPE 0xA380
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#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
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#define INTEL_PCH_ICP2_DEVICE_ID_TYPE 0x3880
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#define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
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#define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080
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#define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x4380
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#define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80
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#define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80
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#define INTEL_PCH_ADP2_DEVICE_ID_TYPE 0x5180
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#define INTEL_PCH_ADP3_DEVICE_ID_TYPE 0x7A00
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#define INTEL_PCH_ADP4_DEVICE_ID_TYPE 0x5480
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#define INTEL_PCH_MTP_DEVICE_ID_TYPE 0x7E00
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#define INTEL_PCH_MTP2_DEVICE_ID_TYPE 0xAE00
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#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
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#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
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#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
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#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
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#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
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#define HAS_PCH_LNL(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LNL)
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#define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
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#define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
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#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
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#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
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#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
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#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
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#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
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#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
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#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
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#define HAS_PCH_LPT_LP(dev_priv) \
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(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
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INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
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#define HAS_PCH_LPT_H(dev_priv) \
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(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
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INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
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#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
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#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
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#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
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#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
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void intel_detect_pch(struct drm_i915_private *dev_priv);
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#endif /* __INTEL_PCH__ */
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