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Xe, is a new driver for Intel GPUs that supports both integrated and discrete platforms starting with Tiger Lake (first Intel Xe Architecture). The code is at a stage where it is already functional and has experimental support for multiple platforms starting from Tiger Lake, with initial support implemented in Mesa (for Iris and Anv, our OpenGL and Vulkan drivers), as well as in NEO (for OpenCL and Level0). The new Xe driver leverages a lot from i915. As for display, the intent is to share the display code with the i915 driver so that there is maximum reuse there. But it is not added in this patch. This initial work is a collaboration of many people and unfortunately the big squashed patch won't fully honor the proper credits. But let's get some git quick stats so we can at least try to preserve some of the credits: Co-developed-by: Matthew Brost <matthew.brost@intel.com> Co-developed-by: Matthew Auld <matthew.auld@intel.com> Co-developed-by: Matt Roper <matthew.d.roper@intel.com> Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Co-developed-by: Francois Dugast <francois.dugast@intel.com> Co-developed-by: Lucas De Marchi <lucas.demarchi@intel.com> Co-developed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Co-developed-by: Philippe Lecluse <philippe.lecluse@intel.com> Co-developed-by: Nirmoy Das <nirmoy.das@intel.com> Co-developed-by: Jani Nikula <jani.nikula@intel.com> Co-developed-by: José Roberto de Souza <jose.souza@intel.com> Co-developed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Co-developed-by: Dave Airlie <airlied@redhat.com> Co-developed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Co-developed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Co-developed-by: Mauro Carvalho Chehab <mchehab@kernel.org> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
220 lines
10 KiB
C
220 lines
10 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2014-2021 Intel Corporation
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*/
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#ifndef _ABI_GUC_ACTIONS_ABI_H
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#define _ABI_GUC_ACTIONS_ABI_H
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/**
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* DOC: HOST2GUC_SELF_CFG
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*
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* This message is used by Host KMD to setup of the `GuC Self Config KLVs`_.
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*
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* This message must be sent as `MMIO HXG Message`_.
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*
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* +---+-------+--------------------------------------------------------------+
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* | | Bits | Description |
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* +===+=======+==============================================================+
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* | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_HOST_ |
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* | +-------+--------------------------------------------------------------+
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* | | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ |
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* | +-------+--------------------------------------------------------------+
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* | | 27:16 | DATA0 = MBZ |
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* | +-------+--------------------------------------------------------------+
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* | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_SELF_CFG` = 0x0508 |
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* +---+-------+--------------------------------------------------------------+
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* | 1 | 31:16 | **KLV_KEY** - KLV key, see `GuC Self Config KLVs`_ |
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* | +-------+--------------------------------------------------------------+
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* | | 15:0 | **KLV_LEN** - KLV length |
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* | | | |
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* | | | - 32 bit KLV = 1 |
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* | | | - 64 bit KLV = 2 |
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* +---+-------+--------------------------------------------------------------+
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* | 2 | 31:0 | **VALUE32** - Bits 31-0 of the KLV value |
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* +---+-------+--------------------------------------------------------------+
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* | 3 | 31:0 | **VALUE64** - Bits 63-32 of the KLV value (**KLV_LEN** = 2) |
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* +---+-------+--------------------------------------------------------------+
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*
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* +---+-------+--------------------------------------------------------------+
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* | | Bits | Description |
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* +===+=======+==============================================================+
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* | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_GUC_ |
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* | +-------+--------------------------------------------------------------+
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* | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_ |
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* | +-------+--------------------------------------------------------------+
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* | | 27:0 | DATA0 = **NUM** - 1 if KLV was parsed, 0 if not recognized |
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* +---+-------+--------------------------------------------------------------+
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*/
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#define GUC_ACTION_HOST2GUC_SELF_CFG 0x0508
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#define HOST2GUC_SELF_CFG_REQUEST_MSG_LEN (GUC_HXG_REQUEST_MSG_MIN_LEN + 3u)
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#define HOST2GUC_SELF_CFG_REQUEST_MSG_0_MBZ GUC_HXG_REQUEST_MSG_0_DATA0
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#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY (0xffff << 16)
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#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN (0xffff << 0)
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#define HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32 GUC_HXG_REQUEST_MSG_n_DATAn
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#define HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64 GUC_HXG_REQUEST_MSG_n_DATAn
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#define HOST2GUC_SELF_CFG_RESPONSE_MSG_LEN GUC_HXG_RESPONSE_MSG_MIN_LEN
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#define HOST2GUC_SELF_CFG_RESPONSE_MSG_0_NUM GUC_HXG_RESPONSE_MSG_0_DATA0
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/**
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* DOC: HOST2GUC_CONTROL_CTB
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*
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* This H2G action allows Vf Host to enable or disable H2G and G2H `CT Buffer`_.
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*
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* This message must be sent as `MMIO HXG Message`_.
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*
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* +---+-------+--------------------------------------------------------------+
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* | | Bits | Description |
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* +===+=======+==============================================================+
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* | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_HOST_ |
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* | +-------+--------------------------------------------------------------+
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* | | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ |
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* | +-------+--------------------------------------------------------------+
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* | | 27:16 | DATA0 = MBZ |
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* | +-------+--------------------------------------------------------------+
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* | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_CONTROL_CTB` = 0x4509 |
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* +---+-------+--------------------------------------------------------------+
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* | 1 | 31:0 | **CONTROL** - control `CTB based communication`_ |
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* | | | |
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* | | | - _`GUC_CTB_CONTROL_DISABLE` = 0 |
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* | | | - _`GUC_CTB_CONTROL_ENABLE` = 1 |
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* +---+-------+--------------------------------------------------------------+
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*
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* +---+-------+--------------------------------------------------------------+
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* | | Bits | Description |
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* +===+=======+==============================================================+
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* | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_GUC_ |
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* | +-------+--------------------------------------------------------------+
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* | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_ |
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* | +-------+--------------------------------------------------------------+
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* | | 27:0 | DATA0 = MBZ |
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* +---+-------+--------------------------------------------------------------+
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*/
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#define GUC_ACTION_HOST2GUC_CONTROL_CTB 0x4509
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#define HOST2GUC_CONTROL_CTB_REQUEST_MSG_LEN (GUC_HXG_REQUEST_MSG_MIN_LEN + 1u)
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#define HOST2GUC_CONTROL_CTB_REQUEST_MSG_0_MBZ GUC_HXG_REQUEST_MSG_0_DATA0
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#define HOST2GUC_CONTROL_CTB_REQUEST_MSG_1_CONTROL GUC_HXG_REQUEST_MSG_n_DATAn
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#define GUC_CTB_CONTROL_DISABLE 0u
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#define GUC_CTB_CONTROL_ENABLE 1u
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#define HOST2GUC_CONTROL_CTB_RESPONSE_MSG_LEN GUC_HXG_RESPONSE_MSG_MIN_LEN
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#define HOST2GUC_CONTROL_CTB_RESPONSE_MSG_0_MBZ GUC_HXG_RESPONSE_MSG_0_DATA0
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/* legacy definitions */
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enum xe_guc_action {
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XE_GUC_ACTION_DEFAULT = 0x0,
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XE_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
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XE_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,
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XE_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
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XE_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
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XE_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
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XE_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x40,
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XE_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
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XE_GUC_ACTION_ENTER_S_STATE = 0x501,
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XE_GUC_ACTION_EXIT_S_STATE = 0x502,
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XE_GUC_ACTION_GLOBAL_SCHED_POLICY_CHANGE = 0x506,
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XE_GUC_ACTION_SCHED_CONTEXT = 0x1000,
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XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET = 0x1001,
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XE_GUC_ACTION_SCHED_CONTEXT_MODE_DONE = 0x1002,
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XE_GUC_ACTION_SCHED_ENGINE_MODE_SET = 0x1003,
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XE_GUC_ACTION_SCHED_ENGINE_MODE_DONE = 0x1004,
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XE_GUC_ACTION_SET_CONTEXT_PRIORITY = 0x1005,
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XE_GUC_ACTION_SET_CONTEXT_EXECUTION_QUANTUM = 0x1006,
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XE_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT = 0x1007,
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XE_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008,
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XE_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
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XE_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES = 0x100B,
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XE_GUC_ACTION_SETUP_PC_GUCRC = 0x3004,
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XE_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
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XE_GUC_ACTION_GET_HWCONFIG = 0x4100,
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XE_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
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XE_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
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XE_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
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XE_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
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XE_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600,
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XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
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XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
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XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
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XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
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XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
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XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,
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XE_GUC_ACTION_ACCESS_COUNTER_NOTIFY = 0x6004,
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XE_GUC_ACTION_TLB_INVALIDATION = 0x7000,
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XE_GUC_ACTION_TLB_INVALIDATION_DONE = 0x7001,
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XE_GUC_ACTION_TLB_INVALIDATION_ALL = 0x7002,
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XE_GUC_ACTION_STATE_CAPTURE_NOTIFICATION = 0x8002,
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XE_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 0x8003,
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XE_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 0x8004,
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XE_GUC_ACTION_NOTIFY_EXCEPTION = 0x8005,
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XE_GUC_ACTION_LIMIT
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};
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enum xe_guc_rc_options {
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XE_GUCRC_HOST_CONTROL,
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XE_GUCRC_FIRMWARE_CONTROL,
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};
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enum xe_guc_preempt_options {
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XE_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4,
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XE_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8,
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};
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enum xe_guc_report_status {
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XE_GUC_REPORT_STATUS_UNKNOWN = 0x0,
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XE_GUC_REPORT_STATUS_ACKED = 0x1,
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XE_GUC_REPORT_STATUS_ERROR = 0x2,
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XE_GUC_REPORT_STATUS_COMPLETE = 0x4,
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};
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enum xe_guc_sleep_state_status {
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XE_GUC_SLEEP_STATE_SUCCESS = 0x1,
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XE_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
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XE_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3
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#define XE_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
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};
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#define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0)
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#define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4
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#define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
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#define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8)
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#define XE_GUC_TLB_INVAL_TYPE_SHIFT 0
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#define XE_GUC_TLB_INVAL_MODE_SHIFT 8
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/* Flush PPC or SMRO caches along with TLB invalidation request */
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#define XE_GUC_TLB_INVAL_FLUSH_CACHE (1 << 31)
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enum xe_guc_tlb_invalidation_type {
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XE_GUC_TLB_INVAL_FULL = 0x0,
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XE_GUC_TLB_INVAL_PAGE_SELECTIVE = 0x1,
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XE_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX = 0x2,
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XE_GUC_TLB_INVAL_GUC = 0x3,
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};
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/*
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* 0: Heavy mode of Invalidation:
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* The pipeline of the engine(s) for which the invalidation is targeted to is
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* blocked, and all the in-flight transactions are guaranteed to be Globally
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* Observed before completing the TLB invalidation
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* 1: Lite mode of Invalidation:
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* TLBs of the targeted engine(s) are immediately invalidated.
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* In-flight transactions are NOT guaranteed to be Globally Observed before
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* completing TLB invalidation.
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* Light Invalidation Mode is to be used only when
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* it can be guaranteed (by SW) that the address translations remain invariant
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* for the in-flight transactions across the TLB invalidation. In other words,
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* this mode can be used when the TLB invalidation is intended to clear out the
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* stale cached translations that are no longer in use. Light Invalidation Mode
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* is much faster than the Heavy Invalidation Mode, as it does not wait for the
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* in-flight transactions to be GOd.
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*/
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enum xe_guc_tlb_inval_mode {
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XE_GUC_TLB_INVAL_MODE_HEAVY = 0x0,
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XE_GUC_TLB_INVAL_MODE_LITE = 0x1,
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};
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#endif
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