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For non-RCS engines, nearly all of the LRC state is composed of MI instructions (specifically MI_LOAD_REGISTER_IMM). Providing a dump interface allows us to verify that the context image layout matches what's documented in the bspec, and also allows us to check whether LRC workarounds are being properly captured by the default state we record at startup. For now, the non-MI instructions found in the RCS and CCS engines will dump as "unknown;" parsing of those will be added in a follow-up patch. v2: - Add raw instruction header as well as decoded meaning. (Lucas) - Check that num_dw isn't greater than remaining_dw for instructions that have a "# dwords" field. (Lucas) - Clarify comment about skipping over ppHWSP. (Lucas) Bspec: 64993 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20231016163449.1300701-13-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
62 lines
2.0 KiB
C
62 lines
2.0 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_MI_COMMANDS_H_
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#define _XE_MI_COMMANDS_H_
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#include "instructions/xe_instr_defs.h"
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/*
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* MI (Memory Interface) commands are supported by all GT engines. They
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* provide general memory operations and command streamer control. MI commands
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* have a command type of 0x0 (MI_COMMAND) in bits 31:29 of the instruction
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* header dword and a specific MI opcode in bits 28:23.
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*/
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#define MI_OPCODE REG_GENMASK(28, 23)
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#define MI_SUBOPCODE REG_GENMASK(22, 17) /* used with MI_EXPANSION */
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#define __MI_INSTR(opcode) \
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(XE_INSTR_MI | REG_FIELD_PREP(MI_OPCODE, opcode))
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#define MI_NOOP __MI_INSTR(0x0)
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#define MI_USER_INTERRUPT __MI_INSTR(0x2)
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#define MI_ARB_CHECK __MI_INSTR(0x5)
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#define MI_ARB_ON_OFF __MI_INSTR(0x8)
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#define MI_ARB_ENABLE REG_BIT(0)
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#define MI_ARB_DISABLE 0x0
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#define MI_BATCH_BUFFER_END __MI_INSTR(0xA)
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#define MI_TOPOLOGY_FILTER __MI_INSTR(0xD)
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#define MI_FORCE_WAKEUP __MI_INSTR(0x1D)
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#define MI_STORE_DATA_IMM __MI_INSTR(0x20)
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#define MI_SDI_GGTT REG_BIT(22)
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#define MI_SDI_LEN_DW GENMASK(9, 0)
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#define MI_SDI_NUM_DW(x) REG_FIELD_PREP(MI_SDI_LEN_DW, (x) + 3 - 2)
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#define MI_SDI_NUM_QW(x) (REG_FIELD_PREP(MI_SDI_LEN_DW, 2 * (x) + 3 - 2) | \
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REG_BIT(21))
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#define MI_LOAD_REGISTER_IMM __MI_INSTR(0x22)
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#define MI_LRI_LRM_CS_MMIO REG_BIT(19)
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#define MI_LRI_MMIO_REMAP_EN REG_BIT(17)
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#define MI_LRI_NUM_REGS(x) XE_INSTR_NUM_DW(2 * (x) + 1)
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#define MI_LRI_FORCE_POSTED REG_BIT(12)
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#define MI_FLUSH_DW __MI_INSTR(0x26)
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#define MI_FLUSH_DW_STORE_INDEX REG_BIT(21)
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#define MI_INVALIDATE_TLB REG_BIT(18)
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#define MI_FLUSH_DW_CCS REG_BIT(16)
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#define MI_FLUSH_DW_OP_STOREDW REG_BIT(14)
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#define MI_FLUSH_DW_LEN_DW REG_GENMASK(5, 0)
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#define MI_FLUSH_IMM_DW REG_FIELD_PREP(MI_FLUSH_DW_LEN_DW, 4 - 2)
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#define MI_FLUSH_IMM_QW REG_FIELD_PREP(MI_FLUSH_DW_LEN_DW, 5 - 2)
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#define MI_FLUSH_DW_USE_GTT REG_BIT(2)
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#define MI_BATCH_BUFFER_START __MI_INSTR(0x31)
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#endif
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