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c6fa06fc4c
Add get ras capability for psp 15.0.8. v2:Remove APU type check and IP version check. Signed-off-by: Jinzhou Su <jinzhou.su@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
364 lines
10 KiB
C
364 lines
10 KiB
C
/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <drm/drm_drv.h>
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#include <linux/vmalloc.h>
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#include "amdgpu.h"
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#include "amdgpu_psp.h"
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#include "amdgpu_ucode.h"
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#include "soc15_common.h"
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#include "psp_v15_0_8.h"
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#include "mp/mp_15_0_8_offset.h"
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#include "mp/mp_15_0_8_sh_mask.h"
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MODULE_FIRMWARE("amdgpu/psp_15_0_8_toc.bin");
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static int psp_v15_0_8_init_microcode(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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char ucode_prefix[30];
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int err = 0;
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amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
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err = psp_init_toc_microcode(psp, ucode_prefix);
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if (err)
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return err;
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return 0;
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}
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static int psp_v15_0_8_ring_stop(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct amdgpu_device *adev = psp->adev;
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if (amdgpu_sriov_vf(adev)) {
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/* Write the ring destroy command*/
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WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
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GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
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0x80000000, 0x80000000, false);
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} else {
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/* Write the ring destroy command*/
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WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64,
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GFX_CTRL_CMD_ID_DESTROY_RINGS);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
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0x80000000, 0x80000000, false);
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}
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return ret;
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}
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static int psp_v15_0_8_ring_create(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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unsigned int psp_ring_reg = 0;
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struct psp_ring *ring = &psp->km_ring;
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struct amdgpu_device *adev = psp->adev;
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if (amdgpu_sriov_vf(adev)) {
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ret = psp_v15_0_8_ring_stop(psp, ring_type);
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if (ret) {
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DRM_ERROR("psp_v14_0_ring_stop_sriov failed!\n");
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return ret;
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}
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/* Write low address of the ring to C2PMSG_102 */
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psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg);
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/* Write high address of the ring to C2PMSG_103 */
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psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg);
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/* Write the ring initialization command to C2PMSG_101 */
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WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
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GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) in C2PMSG_101 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
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0x80000000, 0x8000FFFF, false);
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} else {
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/* Wait for sOS ready for ring creation */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
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0x80000000, 0x80000000, false);
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if (ret) {
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DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
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return ret;
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}
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/* Write low address of the ring to C2PMSG_69 */
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psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg);
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/* Write high address of the ring to C2PMSG_70 */
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psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg);
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/* Write size of ring to C2PMSG_71 */
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psp_ring_reg = ring->ring_size;
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WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg);
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/* Write the ring initialization command to C2PMSG_64 */
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psp_ring_reg = ring_type;
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psp_ring_reg = psp_ring_reg << 16;
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WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) in C2PMSG_64 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
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0x80000000, 0x8000FFFF, false);
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}
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return ret;
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}
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static int psp_v15_0_8_ring_destroy(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct psp_ring *ring = &psp->km_ring;
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struct amdgpu_device *adev = psp->adev;
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ret = psp_v15_0_8_ring_stop(psp, ring_type);
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if (ret)
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DRM_ERROR("Fail to stop psp ring\n");
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amdgpu_bo_free_kernel(&adev->firmware.rbuf,
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&ring->ring_mem_mc_addr,
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(void **)&ring->ring_mem);
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return ret;
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}
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static uint32_t psp_v15_0_8_ring_get_wptr(struct psp_context *psp)
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{
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uint32_t data;
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struct amdgpu_device *adev = psp->adev;
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if (amdgpu_sriov_vf(adev))
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data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102);
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else
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data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67);
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return data;
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}
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static void psp_v15_0_8_ring_set_wptr(struct psp_context *psp, uint32_t value)
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{
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struct amdgpu_device *adev = psp->adev;
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if (amdgpu_sriov_vf(adev)) {
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WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value);
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WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
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GFX_CTRL_CMD_ID_CONSUME_CMD);
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} else
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WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value);
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}
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static bool psp_v15_0_8_get_ras_capability(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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u32 reg_data;
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/* query ras cap should be done from host side */
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if (amdgpu_sriov_vf(adev))
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return false;
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if (!con)
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return false;
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reg_data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_127);
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adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0));
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con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false;
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return true;
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}
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static int psp_v15_0_8_get_fw_type(struct amdgpu_firmware_info *ucode,
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enum psp_gfx_fw_type *type)
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{
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switch (ucode->ucode_id) {
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case AMDGPU_UCODE_ID_CAP:
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*type = GFX_FW_TYPE_CAP;
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break;
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case AMDGPU_UCODE_ID_SDMA0:
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*type = GFX_FW_TYPE_SDMA0;
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break;
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case AMDGPU_UCODE_ID_SDMA1:
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*type = GFX_FW_TYPE_SDMA1;
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break;
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case AMDGPU_UCODE_ID_SDMA2:
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*type = GFX_FW_TYPE_SDMA2;
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break;
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case AMDGPU_UCODE_ID_SDMA3:
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*type = GFX_FW_TYPE_SDMA3;
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break;
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case AMDGPU_UCODE_ID_SDMA4:
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*type = GFX_FW_TYPE_SDMA4;
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break;
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case AMDGPU_UCODE_ID_SDMA5:
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*type = GFX_FW_TYPE_SDMA5;
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break;
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case AMDGPU_UCODE_ID_SDMA6:
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*type = GFX_FW_TYPE_SDMA6;
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break;
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case AMDGPU_UCODE_ID_SDMA7:
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*type = GFX_FW_TYPE_SDMA7;
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break;
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case AMDGPU_UCODE_ID_CP_MES:
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*type = GFX_FW_TYPE_RS64_MES;
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break;
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case AMDGPU_UCODE_ID_CP_MES_DATA:
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*type = GFX_FW_TYPE_RS64_MES_STACK;
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break;
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case AMDGPU_UCODE_ID_CP_MES1:
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*type = GFX_FW_TYPE_RS64_KIQ;
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break;
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case AMDGPU_UCODE_ID_CP_MES1_DATA:
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*type = GFX_FW_TYPE_RS64_KIQ_STACK;
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break;
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case AMDGPU_UCODE_ID_RLC_P:
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*type = GFX_FW_TYPE_RLC_P;
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break;
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case AMDGPU_UCODE_ID_RLC_V:
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*type = GFX_FW_TYPE_RLC_V;
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break;
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case AMDGPU_UCODE_ID_RLC_G:
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*type = GFX_FW_TYPE_RLC_G;
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break;
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case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
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*type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
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break;
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case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
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*type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
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break;
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case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
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*type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
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break;
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case AMDGPU_UCODE_ID_RLC_IRAM:
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*type = GFX_FW_TYPE_RLC_IRAM;
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break;
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case AMDGPU_UCODE_ID_RLC_DRAM:
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*type = GFX_FW_TYPE_RLC_DRAM_BOOT;
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break;
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case AMDGPU_UCODE_ID_RLC_IRAM_1:
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*type = GFX_FW_TYPE_RLX6_UCODE_CORE1;
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break;
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case AMDGPU_UCODE_ID_RLC_DRAM_1:
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*type = GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1;
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break;
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case AMDGPU_UCODE_ID_SMC:
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*type = GFX_FW_TYPE_SMU;
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break;
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case AMDGPU_UCODE_ID_PPTABLE:
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*type = GFX_FW_TYPE_PPTABLE;
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break;
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case AMDGPU_UCODE_ID_VCN:
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*type = GFX_FW_TYPE_VCN;
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break;
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case AMDGPU_UCODE_ID_VCN1:
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*type = GFX_FW_TYPE_VCN1;
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break;
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case AMDGPU_UCODE_ID_VCN0_RAM:
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*type = GFX_FW_TYPE_VCN0_RAM;
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break;
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case AMDGPU_UCODE_ID_VCN1_RAM:
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*type = GFX_FW_TYPE_VCN1_RAM;
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break;
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case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
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case AMDGPU_UCODE_ID_SDMA_RS64:
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*type = GFX_FW_TYPE_SDMA0;
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break;
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case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
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*type = GFX_FW_TYPE_SDMA_UCODE_TH1;
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break;
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case AMDGPU_UCODE_ID_IMU_I:
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*type = GFX_FW_TYPE_IMU_I;
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break;
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case AMDGPU_UCODE_ID_IMU_D:
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*type = GFX_FW_TYPE_IMU_D;
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break;
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case AMDGPU_UCODE_ID_CP_RS64_MEC:
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*type = GFX_FW_TYPE_RS64_MEC;
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break;
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case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
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*type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
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break;
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case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
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*type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
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break;
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case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
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*type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
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break;
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case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
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*type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
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break;
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case AMDGPU_UCODE_ID_UMSCH_MM_UCODE:
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*type = GFX_FW_TYPE_UMSCH_UCODE;
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break;
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case AMDGPU_UCODE_ID_UMSCH_MM_DATA:
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*type = GFX_FW_TYPE_UMSCH_DATA;
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break;
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case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER:
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*type = GFX_FW_TYPE_UMSCH_CMD_BUFFER;
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break;
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case AMDGPU_UCODE_ID_P2S_TABLE:
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*type = GFX_FW_TYPE_P2S_TABLE;
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break;
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case AMDGPU_UCODE_ID_MAXIMUM:
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default:
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return -EINVAL;
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}
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return 0;
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}
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static const struct psp_funcs psp_v15_0_8_funcs = {
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.init_microcode = psp_v15_0_8_init_microcode,
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.ring_create = psp_v15_0_8_ring_create,
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.ring_stop = psp_v15_0_8_ring_stop,
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.ring_destroy = psp_v15_0_8_ring_destroy,
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.ring_get_wptr = psp_v15_0_8_ring_get_wptr,
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.ring_set_wptr = psp_v15_0_8_ring_set_wptr,
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.get_fw_type = psp_v15_0_8_get_fw_type,
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.get_ras_capability = psp_v15_0_8_get_ras_capability,
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};
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void psp_v15_0_8_set_psp_funcs(struct psp_context *psp)
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{
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psp->funcs = &psp_v15_0_8_funcs;
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}
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