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When a bridge window contains big and small resource(s), the small resource(s) may not amount to the half of the size of the big resource which would allow calculate_head_align() to shrink the head alignment. This results in always placing the small resource(s) after the big resource. In general, it would be good to be able to place the small resource(s) before the big resource to achieve better utilization of the address space. In the cases where the large resource can only fit at the end of the window, it is even required. However, carrying the information over from pbus_size_mem() and calculate_head_align() to __pci_assign_resource() and pcibios_align_resource() is not easy with the current data structures. A somewhat hacky way to move the non-aligning tail part to the head is possible within pcibios_align_resource(). The free space between the start of the free space span and the aligned start address can be compared with the non-aligning remainder of the size. If the free space is larger than the remainder, placing the remainder before the start address is possible. This relocation should generally work, because PCI resources consist only power-of-2 atoms. Various arch requirements may still need to override the relocation, so the relocation is only applied selectively in such cases. Closes: https://bugzilla.kernel.org/show_bug.cgi?id=221205 Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Xifer <xiferdev@gmail.com> Link: https://patch.msgid.link/20260324165633.4583-10-ilpo.jarvinen@linux.intel.com
82 lines
2.1 KiB
C
82 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* pci.c -- basic PCI support code
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*
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* (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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/*
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* From arch/i386/kernel/pci-i386.c:
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*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*
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* Why? Because some silly external IO cards only decode
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* the low 10 bits of the IO address. The 0x00-0xff region
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* is reserved for motherboard devices that decode all 16
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* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
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* but we want to try to avoid allocating at 0x2900-0x2bff
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* which might be mirrored at 0x0100-0x03ff..
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*/
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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const struct resource *empty_res,
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resource_size_t size,
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resource_size_t align)
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{
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struct pci_dev *dev = data;
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resource_size_t start = res->start;
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if ((res->flags & IORESOURCE_IO) && (start & 0x300))
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start = (start + 0x3ff) & ~0x3ff;
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if (res->flags & IORESOURCE_MEM)
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return pci_align_resource(dev, res, empty_res, size, align);
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return start;
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}
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/*
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* This is taken from the ARM code for this.
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*/
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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u16 cmd, newcmd;
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int ret;
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ret = pci_enable_resources(dev, mask);
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if (ret < 0)
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return ret;
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/*
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* Bridges (eg, cardbus bridges) need to be fully enabled
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*/
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if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) {
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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newcmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
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if (newcmd != cmd) {
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pr_info("PCI: enabling bridge %s (0x%04x -> 0x%04x)\n",
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pci_name(dev), cmd, newcmd);
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pci_write_config_word(dev, PCI_COMMAND, newcmd);
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}
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}
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return 0;
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}
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void pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev;
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list_for_each_entry(dev, &bus->devices, bus_list) {
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 32);
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}
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}
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