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The J721E SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable lower system costs of automotive applications such as infotainment, cluster, premium Audio, Gateway, industrial and a range of broad market applications. This SoC is designed around reducing the system cost by eliminating the need of an external system MCU and is targeted towards ASIL-B/C certification/requirements in addition to allowing complex software and system use-cases. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP, Two C66x floating point DSPs. * 3D GPU PowerVR Rogue 8XE GE8430 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual PRUs and dual RTUs * Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and up to two DPI interfaces. * Integrated Ethernet switch supporting up to a total of 8 external ports in addition to legacy Ethernet switch of up to 2 ports. * System MMU (SMMU) Version 3.0 and advanced virtualisation capabilities. * Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems, 16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS * Centralized System Controller for Security, Power, and Resource Management (DMSC) See J721E Technical Reference Manual (SPRUIL1, May 2019) for further details: http://www.ti.com/lit/pdf/spruil1 Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Tero Kristo <t-kristo@ti.com>
27 lines
663 B
Plaintext
27 lines
663 B
Plaintext
Texas Instruments K3 Multicore SoC architecture device tree bindings
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Platforms based on Texas Instruments K3 Multicore SoC architecture
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shall follow the following scheme:
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SoCs
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----
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Each device tree root node must specify which exact SoC in K3 Multicore SoC
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architecture it uses, using one of the following compatible values:
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- AM654
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compatible = "ti,am654";
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- J721E
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compatible = "ti,j721e";
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Boards
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------
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In addition, each device tree root node must specify which one or more
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of the following board-specific compatible values:
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- AM654 EVM
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compatible = "ti,am654-evm", "ti,am654";
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