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a1a702090d
Add ref-sync-sources phandle-array property to the dpll-pin schema allowing board designers to declare which input pins can serve as sync sources in a Reference-Sync pair. A Ref-Sync pair consists of a clock reference and a low-frequency sync signal where the DPLL locks to the clock but phase-aligns to the sync reference. Update both examples in the Microchip ZL3073x binding to demonstrate the new property with a 1 PPS sync source paired to a clock source. Reviewed-by: Petr Oros <poros@redhat.com> Reviewed-by: Prathosh Satish <Prathosh.Satish@microchip.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ivan Vecera <ivecera@redhat.com> Link: https://patch.msgid.link/20260408102716.443099-5-ivecera@redhat.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
132 lines
3.1 KiB
YAML
132 lines
3.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dpll/microchip,zl30731.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip Azurite DPLL device
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maintainers:
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- Ivan Vecera <ivecera@redhat.com>
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description:
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Microchip Azurite DPLL (ZL3073x) is a family of DPLL devices that
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provides up to 5 independent DPLL channels, up to 10 differential or
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single-ended inputs and 10 differential or 20 single-ended outputs.
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These devices support both I2C and SPI interfaces.
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properties:
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compatible:
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enum:
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- microchip,zl30731
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- microchip,zl30732
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- microchip,zl30733
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- microchip,zl30734
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- microchip,zl30735
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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allOf:
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- $ref: /schemas/dpll/dpll-device.yaml#
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- $ref: /schemas/spi/spi-peripheral-props.yaml#
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unevaluatedProperties: false
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examples:
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- |
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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dpll@70 {
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compatible = "microchip,zl30732";
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reg = <0x70>;
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dpll-types = "pps", "eec";
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input-pins {
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#address-cells = <1>;
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#size-cells = <0>;
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sync0: pin@0 { /* REF0P - 1 PPS sync source */
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reg = <0>;
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connection-type = "ext";
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label = "SMA1";
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supported-frequencies-hz = /bits/ 64 <1>;
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};
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pin@1 { /* REF0N - clock source, can pair with sync0 */
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reg = <1>;
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connection-type = "ext";
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label = "SMA2";
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supported-frequencies-hz = /bits/ 64 <10000 10000000>;
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ref-sync-sources = <&sync0>;
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};
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};
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output-pins {
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#address-cells = <1>;
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#size-cells = <0>;
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pin@3 { /* OUT1N */
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reg = <3>;
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connection-type = "gnss";
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esync-control;
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label = "Output 1";
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supported-frequencies-hz = /bits/ 64 <1 10000>;
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};
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};
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};
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};
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- |
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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dpll@70 {
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compatible = "microchip,zl30731";
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reg = <0x70>;
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spi-max-frequency = <12500000>;
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dpll-types = "pps";
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input-pins {
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#address-cells = <1>;
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#size-cells = <0>;
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sync1: pin@0 { /* REF0P - 1 PPS sync source */
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reg = <0>;
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connection-type = "gnss";
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label = "GNSS_1PPS_IN";
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supported-frequencies-hz = /bits/ 64 <1>;
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};
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pin@1 { /* REF0N - clock source */
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reg = <1>;
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connection-type = "gnss";
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label = "GNSS_10M_IN";
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supported-frequencies-hz = /bits/ 64 <10000000>;
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ref-sync-sources = <&sync1>;
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};
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};
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output-pins {
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#address-cells = <1>;
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#size-cells = <0>;
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pin@3 { /* OUT1N */
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reg = <3>;
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connection-type = "gnss";
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esync-control;
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label = "Output 1";
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supported-frequencies-hz = /bits/ 64 <1 10000>;
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};
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};
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};
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};
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...
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