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8838bb185e
The ports in the example device tree should not have a 'label' property. Labels for all user ports have been removed from an earlier submission, but this was overlooked in the case of the CPU port. Remove 'cpu' port label from the example. Suggested-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/61579de297eb636ec5f1e6c97d453e26abb0625d.1772507210.git.daniel@makrotopia.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
161 lines
3.8 KiB
YAML
161 lines
3.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/dsa/maxlinear,mxl862xx.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MaxLinear MxL862xx Ethernet Switch Family
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maintainers:
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- Daniel Golle <daniel@makrotopia.org>
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description:
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The MaxLinear MxL862xx switch family are multi-port Ethernet switches with
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integrated 2.5GE PHYs. The MxL86252 has five PHY ports and the MxL86282
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has eight PHY ports. Both models come with two 10 Gigabit/s SerDes
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interfaces to be used to connect external PHYs or SFP cages, or as CPU
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port.
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allOf:
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- $ref: dsa.yaml#/$defs/ethernet-ports
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properties:
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compatible:
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enum:
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- maxlinear,mxl86252
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- maxlinear,mxl86282
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reg:
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maxItems: 1
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description: MDIO address of the switch
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mdio:
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$ref: /schemas/net/mdio.yaml#
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unevaluatedProperties: false
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required:
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- compatible
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- mdio
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- reg
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unevaluatedProperties: false
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examples:
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- |
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch@0 {
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compatible = "maxlinear,mxl86282";
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reg = <0>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* Microcontroller port */
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port@0 {
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reg = <0>;
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status = "disabled";
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};
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port@1 {
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reg = <1>;
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phy-handle = <&phy0>;
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phy-mode = "internal";
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};
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port@2 {
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reg = <2>;
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phy-handle = <&phy1>;
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phy-mode = "internal";
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};
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port@3 {
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reg = <3>;
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phy-handle = <&phy2>;
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phy-mode = "internal";
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};
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port@4 {
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reg = <4>;
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phy-handle = <&phy3>;
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phy-mode = "internal";
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};
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port@5 {
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reg = <5>;
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phy-handle = <&phy4>;
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phy-mode = "internal";
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};
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port@6 {
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reg = <6>;
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phy-handle = <&phy5>;
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phy-mode = "internal";
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};
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port@7 {
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reg = <7>;
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phy-handle = <&phy6>;
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phy-mode = "internal";
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};
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port@8 {
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reg = <8>;
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phy-handle = <&phy7>;
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phy-mode = "internal";
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};
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port@9 {
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reg = <9>;
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ethernet = <&gmac0>;
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phy-mode = "usxgmii";
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fixed-link {
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speed = <10000>;
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full-duplex;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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};
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phy4: ethernet-phy@4 {
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reg = <4>;
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};
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phy5: ethernet-phy@5 {
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reg = <5>;
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};
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phy6: ethernet-phy@6 {
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reg = <6>;
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};
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phy7: ethernet-phy@7 {
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reg = <7>;
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};
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};
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};
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};
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