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This MDIO hardware is based on a Microsemi design supported in Linux by mdio-mscc-miim.c. However, The register interface is completely different with pic64hpsc, hence the need for separate documentation. The hardware supports C22 and C45. The documentation recommends an input clock of 156.25MHz and a prescaler of 39, which yields an MDIO clock of 1.95MHz. The hardware supports an interrupt pin to signal transaction completion which is not strictly needed as the software can also poll a "TRIGGER" bit for this. Signed-off-by: Charles Perry <charles.perry@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260408131821.1145334-2-charles.perry@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
69 lines
1.4 KiB
YAML
69 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/microchip,pic64hpsc-mdio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip PIC64-HPSC/HX MDIO controller
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maintainers:
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- Charles Perry <charles.perry@microchip.com>
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description:
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This is the MDIO bus controller present in Microchip PIC64-HPSC/HX SoCs. It
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supports C22 and C45 register access and is named "MDIO Initiator" in the
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documentation.
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allOf:
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- $ref: mdio.yaml#
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properties:
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compatible:
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oneOf:
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- const: microchip,pic64hpsc-mdio
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- items:
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- const: microchip,pic64hx-mdio
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- const: microchip,pic64hpsc-mdio
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-frequency:
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default: 2500000
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- interrupts
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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mdio@4000c21e000 {
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compatible = "microchip,pic64hpsc-mdio";
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reg = <0x400 0x0c21e000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&svc_clk>;
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interrupt-parent = <&saplic0>;
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interrupts = <168 IRQ_TYPE_LEVEL_HIGH>;
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ethernet-phy@0 {
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reg = <0>;
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};
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};
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};
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