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Since IMX serial SOCs support low bus freq mode, some clocks freq may change to save power. I2C needs to check the clock source and update the divider. For example: i.MX6SL I2C clk is from IPG_PERCLK which is sourced from IPG_CLK. Under normal operation, IPG_CLK is 66MHz, ipg_perclk is at 22MHz. In low bus freq mode, IPG_CLK is at 12MHz and IPG_PERCLK is down to 4MHz. So the I2C driver must update the divider register for each transaction when the current IPG_PERCLK is not equal to the clock of previous transaction. Signed-off-by: Fugang Duan <B38611@freescale.com> [wsa: removed an outdated comment and simplified debug output] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>