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ef2964f11e
Currently Tyr uses rustfmt style for imports, but the kernel uses a vertical layout that makes it easier to resolve conflicts and rebase. Import guidelines are documented here: https://docs.kernel.org/rust/coding-guidelines.html#imports Change all of Tyr's imports to use the vertical layout. This will ease the introduction of additional Tyr patches upstream. There should be no functional changes in this patch. Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Deborah Brouwer <deborah.brouwer@collabora.com> Link: https://patch.msgid.link/20260223203833.207955-1-deborah.brouwer@collabora.com Signed-off-by: Alice Ryhl <aliceryhl@google.com>
114 lines
4.8 KiB
Rust
114 lines
4.8 KiB
Rust
// SPDX-License-Identifier: GPL-2.0 or MIT
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// We don't expect that all the registers and fields will be used, even in the
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// future.
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//
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// Nevertheless, it is useful to have most of them defined, like the C driver
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// does.
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#![allow(dead_code)]
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use kernel::{
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bits::bit_u32,
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device::{
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Bound,
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Device, //
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},
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devres::Devres,
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io::Io,
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prelude::*, //
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};
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use crate::driver::IoMem;
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/// Represents a register in the Register Set
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///
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/// TODO: Replace this with the Nova `register!()` macro when it is available.
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/// In particular, this will automatically give us 64bit register reads and
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/// writes.
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pub(crate) struct Register<const OFFSET: usize>;
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impl<const OFFSET: usize> Register<OFFSET> {
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#[inline]
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pub(crate) fn read(&self, dev: &Device<Bound>, iomem: &Devres<IoMem>) -> Result<u32> {
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let value = (*iomem).access(dev)?.read32(OFFSET);
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Ok(value)
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}
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#[inline]
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pub(crate) fn write(&self, dev: &Device<Bound>, iomem: &Devres<IoMem>, value: u32) -> Result {
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(*iomem).access(dev)?.write32(value, OFFSET);
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Ok(())
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}
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}
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pub(crate) const GPU_ID: Register<0x0> = Register;
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pub(crate) const GPU_L2_FEATURES: Register<0x4> = Register;
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pub(crate) const GPU_CORE_FEATURES: Register<0x8> = Register;
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pub(crate) const GPU_CSF_ID: Register<0x1c> = Register;
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pub(crate) const GPU_REVID: Register<0x280> = Register;
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pub(crate) const GPU_TILER_FEATURES: Register<0xc> = Register;
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pub(crate) const GPU_MEM_FEATURES: Register<0x10> = Register;
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pub(crate) const GPU_MMU_FEATURES: Register<0x14> = Register;
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pub(crate) const GPU_AS_PRESENT: Register<0x18> = Register;
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pub(crate) const GPU_IRQ_RAWSTAT: Register<0x20> = Register;
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pub(crate) const GPU_IRQ_RAWSTAT_FAULT: u32 = bit_u32(0);
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pub(crate) const GPU_IRQ_RAWSTAT_PROTECTED_FAULT: u32 = bit_u32(1);
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pub(crate) const GPU_IRQ_RAWSTAT_RESET_COMPLETED: u32 = bit_u32(8);
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pub(crate) const GPU_IRQ_RAWSTAT_POWER_CHANGED_SINGLE: u32 = bit_u32(9);
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pub(crate) const GPU_IRQ_RAWSTAT_POWER_CHANGED_ALL: u32 = bit_u32(10);
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pub(crate) const GPU_IRQ_RAWSTAT_CLEAN_CACHES_COMPLETED: u32 = bit_u32(17);
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pub(crate) const GPU_IRQ_RAWSTAT_DOORBELL_STATUS: u32 = bit_u32(18);
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pub(crate) const GPU_IRQ_RAWSTAT_MCU_STATUS: u32 = bit_u32(19);
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pub(crate) const GPU_IRQ_CLEAR: Register<0x24> = Register;
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pub(crate) const GPU_IRQ_MASK: Register<0x28> = Register;
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pub(crate) const GPU_IRQ_STAT: Register<0x2c> = Register;
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pub(crate) const GPU_CMD: Register<0x30> = Register;
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pub(crate) const GPU_CMD_SOFT_RESET: u32 = 1 | (1 << 8);
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pub(crate) const GPU_CMD_HARD_RESET: u32 = 1 | (2 << 8);
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pub(crate) const GPU_THREAD_FEATURES: Register<0xac> = Register;
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pub(crate) const GPU_THREAD_MAX_THREADS: Register<0xa0> = Register;
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pub(crate) const GPU_THREAD_MAX_WORKGROUP_SIZE: Register<0xa4> = Register;
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pub(crate) const GPU_THREAD_MAX_BARRIER_SIZE: Register<0xa8> = Register;
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pub(crate) const GPU_TEXTURE_FEATURES0: Register<0xb0> = Register;
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pub(crate) const GPU_SHADER_PRESENT_LO: Register<0x100> = Register;
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pub(crate) const GPU_SHADER_PRESENT_HI: Register<0x104> = Register;
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pub(crate) const GPU_TILER_PRESENT_LO: Register<0x110> = Register;
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pub(crate) const GPU_TILER_PRESENT_HI: Register<0x114> = Register;
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pub(crate) const GPU_L2_PRESENT_LO: Register<0x120> = Register;
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pub(crate) const GPU_L2_PRESENT_HI: Register<0x124> = Register;
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pub(crate) const L2_READY_LO: Register<0x160> = Register;
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pub(crate) const L2_READY_HI: Register<0x164> = Register;
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pub(crate) const L2_PWRON_LO: Register<0x1a0> = Register;
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pub(crate) const L2_PWRON_HI: Register<0x1a4> = Register;
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pub(crate) const L2_PWRTRANS_LO: Register<0x220> = Register;
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pub(crate) const L2_PWRTRANS_HI: Register<0x204> = Register;
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pub(crate) const L2_PWRACTIVE_LO: Register<0x260> = Register;
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pub(crate) const L2_PWRACTIVE_HI: Register<0x264> = Register;
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pub(crate) const MCU_CONTROL: Register<0x700> = Register;
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pub(crate) const MCU_CONTROL_ENABLE: u32 = 1;
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pub(crate) const MCU_CONTROL_AUTO: u32 = 2;
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pub(crate) const MCU_CONTROL_DISABLE: u32 = 0;
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pub(crate) const MCU_STATUS: Register<0x704> = Register;
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pub(crate) const MCU_STATUS_DISABLED: u32 = 0;
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pub(crate) const MCU_STATUS_ENABLED: u32 = 1;
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pub(crate) const MCU_STATUS_HALT: u32 = 2;
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pub(crate) const MCU_STATUS_FATAL: u32 = 3;
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pub(crate) const GPU_COHERENCY_FEATURES: Register<0x300> = Register;
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pub(crate) const JOB_IRQ_RAWSTAT: Register<0x1000> = Register;
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pub(crate) const JOB_IRQ_CLEAR: Register<0x1004> = Register;
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pub(crate) const JOB_IRQ_MASK: Register<0x1008> = Register;
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pub(crate) const JOB_IRQ_STAT: Register<0x100c> = Register;
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pub(crate) const JOB_IRQ_GLOBAL_IF: u32 = bit_u32(31);
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pub(crate) const MMU_IRQ_RAWSTAT: Register<0x2000> = Register;
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pub(crate) const MMU_IRQ_CLEAR: Register<0x2004> = Register;
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pub(crate) const MMU_IRQ_MASK: Register<0x2008> = Register;
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pub(crate) const MMU_IRQ_STAT: Register<0x200c> = Register;
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