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The auxiliary device registration was using a hardcoded ID of 0, which caused probe() to fail on multi-GPU systems with: sysfs: cannot create duplicate filename '/bus/auxiliary/devices/NovaCore.nova-drm.0' Fix this by using an atomic counter to generate unique IDs for each GPU's aux device registration. The TODO item to eventually use XArray for recycling aux device IDs is retained, but for now, this works very nicely. This has the side effect of making debugfs[1] work on multi-GPU systems. [1] https://lore.kernel.org/20260203224757.871729-1-ttabi@nvidia.com Reviewed-by: Gary Guo <gary@garyguo.net> Signed-off-by: John Hubbard <jhubbard@nvidia.com> Link: https://patch.msgid.link/20260221020952.412352-2-jhubbard@nvidia.com [ Use LKMM atomics; inline and slightly reword TODO comment. - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
115 lines
3.2 KiB
Rust
115 lines
3.2 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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use kernel::{
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auxiliary,
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device::Core,
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devres::Devres,
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dma::Device,
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dma::DmaMask,
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pci,
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pci::{
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Class,
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ClassMask,
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Vendor, //
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},
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prelude::*,
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sizes::SZ_16M,
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sync::{
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atomic::{
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Atomic,
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Relaxed, //
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},
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Arc,
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},
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};
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use crate::gpu::Gpu;
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/// Counter for generating unique auxiliary device IDs.
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static AUXILIARY_ID_COUNTER: Atomic<u32> = Atomic::new(0);
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#[pin_data]
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pub(crate) struct NovaCore {
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#[pin]
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pub(crate) gpu: Gpu,
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#[pin]
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_reg: Devres<auxiliary::Registration>,
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}
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const BAR0_SIZE: usize = SZ_16M;
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// For now we only support Ampere which can use up to 47-bit DMA addresses.
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//
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// TODO: Add an abstraction for this to support newer GPUs which may support
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// larger DMA addresses. Limiting these GPUs to smaller address widths won't
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// have any adverse affects, unless installed on systems which require larger
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// DMA addresses. These systems should be quite rare.
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const GPU_DMA_BITS: u32 = 47;
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pub(crate) type Bar0 = pci::Bar<BAR0_SIZE>;
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kernel::pci_device_table!(
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PCI_TABLE,
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MODULE_PCI_TABLE,
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<NovaCore as pci::Driver>::IdInfo,
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[
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// Modern NVIDIA GPUs will show up as either VGA or 3D controllers.
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(
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pci::DeviceId::from_class_and_vendor(
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Class::DISPLAY_VGA,
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ClassMask::ClassSubclass,
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Vendor::NVIDIA
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),
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()
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),
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(
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pci::DeviceId::from_class_and_vendor(
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Class::DISPLAY_3D,
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ClassMask::ClassSubclass,
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Vendor::NVIDIA
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),
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()
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),
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]
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);
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impl pci::Driver for NovaCore {
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type IdInfo = ();
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const ID_TABLE: pci::IdTable<Self::IdInfo> = &PCI_TABLE;
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fn probe(pdev: &pci::Device<Core>, _info: &Self::IdInfo) -> impl PinInit<Self, Error> {
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pin_init::pin_init_scope(move || {
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dev_dbg!(pdev, "Probe Nova Core GPU driver.\n");
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pdev.enable_device_mem()?;
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pdev.set_master();
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// SAFETY: No concurrent DMA allocations or mappings can be made because
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// the device is still being probed and therefore isn't being used by
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// other threads of execution.
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unsafe { pdev.dma_set_mask_and_coherent(DmaMask::new::<GPU_DMA_BITS>())? };
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let bar = Arc::pin_init(
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pdev.iomap_region_sized::<BAR0_SIZE>(0, c"nova-core/bar0"),
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GFP_KERNEL,
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)?;
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Ok(try_pin_init!(Self {
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gpu <- Gpu::new(pdev, bar.clone(), bar.access(pdev.as_ref())?),
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_reg <- auxiliary::Registration::new(
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pdev.as_ref(),
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c"nova-drm",
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// TODO[XARR]: Use XArray or perhaps IDA for proper ID allocation/recycling. For
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// now, use a simple atomic counter that never recycles IDs.
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AUXILIARY_ID_COUNTER.fetch_add(1, Relaxed),
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crate::MODULE_NAME
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),
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}))
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})
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}
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fn unbind(pdev: &pci::Device<Core>, this: Pin<&Self>) {
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this.gpu.unbind(pdev.as_ref());
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}
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}
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