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38f7e5450e
Convert all PFALCON, PFALCON2 and PRISCV registers to use the kernel's register macro and update the code accordingly. Because they rely on the same types to implement relative registers, they need to be updated in lockstep. nova-core's local register macro is now unused, so remove it. Reviewed-by: Gary Guo <gary@garyguo.net> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20260325-b4-nova-register-v4-8-bdf172f0f6ca@nvidia.com [acourbot@nvidia.com: remove unused import.] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
61 lines
1.4 KiB
Rust
61 lines
1.4 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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use kernel::{
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io::{
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poll::read_poll_timeout,
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register::{
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RegisterBase,
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WithBase, //
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},
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Io,
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},
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prelude::*,
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time::Delta, //
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};
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use crate::{
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driver::Bar0,
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falcon::{
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Falcon,
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FalconEngine,
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PFalcon2Base,
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PFalconBase, //
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},
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regs,
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};
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/// Type specifying the `Gsp` falcon engine. Cannot be instantiated.
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pub(crate) struct Gsp(());
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impl RegisterBase<PFalconBase> for Gsp {
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const BASE: usize = 0x00110000;
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}
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impl RegisterBase<PFalcon2Base> for Gsp {
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const BASE: usize = 0x00111000;
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}
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impl FalconEngine for Gsp {}
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impl Falcon<Gsp> {
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/// Clears the SWGEN0 bit in the Falcon's IRQ status clear register to
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/// allow GSP to signal CPU for processing new messages in message queue.
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pub(crate) fn clear_swgen0_intr(&self, bar: &Bar0) {
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bar.write(
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WithBase::of::<Gsp>(),
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regs::NV_PFALCON_FALCON_IRQSCLR::zeroed().with_swgen0(true),
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);
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}
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/// Checks if GSP reload/resume has completed during the boot process.
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pub(crate) fn check_reload_completed(&self, bar: &Bar0, timeout: Delta) -> Result<bool> {
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read_poll_timeout(
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|| Ok(bar.read(regs::NV_PGC6_BSI_SECURE_SCRATCH_14)),
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|val| val.boot_stage_3_handoff(),
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Delta::ZERO,
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timeout,
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)
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.map(|_| true)
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}
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}
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