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ffabad08e4
Convert all GC6 registers to use the kernel's register macro and update the code accordingly. Reviewed-by: Eliot Courtney <ecourtney@nvidia.com> Reviewed-by: Gary Guo <gary@garyguo.net> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20260325-b4-nova-register-v4-5-bdf172f0f6ca@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
42 lines
852 B
Rust
42 lines
852 B
Rust
// SPDX-License-Identifier: GPL-2.0
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use kernel::{
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io::Io,
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prelude::*, //
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};
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use crate::{
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driver::Bar0,
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fb::hal::FbHal,
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regs, //
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};
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fn vidmem_size_ga102(bar: &Bar0) -> u64 {
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bar.read(regs::NV_USABLE_FB_SIZE_IN_MB).usable_fb_size()
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}
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struct Ga102;
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impl FbHal for Ga102 {
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fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 {
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super::ga100::read_sysmem_flush_page_ga100(bar)
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}
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fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result {
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super::ga100::write_sysmem_flush_page_ga100(bar, addr);
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Ok(())
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}
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fn supports_display(&self, bar: &Bar0) -> bool {
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super::ga100::display_enabled_ga100(bar)
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}
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fn vidmem_size(&self, bar: &Bar0) -> u64 {
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vidmem_size_ga102(bar)
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}
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}
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const GA102: Ga102 = Ga102;
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pub(super) const GA102_HAL: &dyn FbHal = &GA102;
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