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1a8f58c5e1
Convert all FUSE registers to use the kernel's register macro and update the code accordingly. Reviewed-by: Eliot Courtney <ecourtney@nvidia.com> Reviewed-by: Gary Guo <gary@garyguo.net> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20260325-b4-nova-register-v4-6-bdf172f0f6ca@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
63 lines
1.6 KiB
Rust
63 lines
1.6 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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use kernel::{
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io::Io,
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prelude::*, //
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};
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use crate::{
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driver::Bar0,
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fb::hal::FbHal,
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regs, //
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};
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/// Shift applied to the sysmem address before it is written into `NV_PFB_NISO_FLUSH_SYSMEM_ADDR`,
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/// to be used by HALs.
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pub(super) const FLUSH_SYSMEM_ADDR_SHIFT: u32 = 8;
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pub(super) fn read_sysmem_flush_page_gm107(bar: &Bar0) -> u64 {
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u64::from(bar.read(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT
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}
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pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0, addr: u64) -> Result {
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// Check that the address doesn't overflow the receiving 32-bit register.
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u32::try_from(addr >> FLUSH_SYSMEM_ADDR_SHIFT)
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.map_err(|_| EINVAL)
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.map(|addr| {
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bar.write_reg(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::zeroed().with_adr_39_08(addr))
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})
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}
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pub(super) fn display_enabled_gm107(bar: &Bar0) -> bool {
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!bar.read(regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY)
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.display_disabled()
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}
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pub(super) fn vidmem_size_gp102(bar: &Bar0) -> u64 {
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bar.read(regs::NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE)
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.usable_fb_size()
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}
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struct Tu102;
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impl FbHal for Tu102 {
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fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 {
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read_sysmem_flush_page_gm107(bar)
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}
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fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result {
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write_sysmem_flush_page_gm107(bar, addr)
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}
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fn supports_display(&self, bar: &Bar0) -> bool {
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display_enabled_gm107(bar)
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}
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fn vidmem_size(&self, bar: &Bar0) -> u64 {
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vidmem_size_gp102(bar)
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}
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}
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const TU102: Tu102 = Tu102;
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pub(super) const TU102_HAL: &dyn FbHal = &TU102;
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