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90930b637d
Keep the convention of naming vlv_clock* instead of vlv_*_clock. Signed-off-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://lore.kernel.org/r/20250919215413.1006296-1-michal.grzelak@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
89 lines
2.4 KiB
C
89 lines
2.4 KiB
C
// SPDX-License-Identifier: MIT
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/* Copyright © 2025 Intel Corporation */
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#include <drm/drm_print.h>
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#include "intel_display_core.h"
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#include "intel_display_types.h"
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#include "vlv_clock.h"
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#include "vlv_sideband.h"
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/*
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* FIXME: The caching of hpll_freq and czclk_freq relies on the first calls
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* occurring at a time when they can actually be read. This appears to be the
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* case, but is somewhat fragile. Make the initialization explicit at a point
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* where they can be reliably read.
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*/
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/* returns HPLL frequency in kHz */
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int vlv_clock_get_hpll_vco(struct drm_device *drm)
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{
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struct intel_display *display = to_intel_display(drm);
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int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
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if (!display->vlv_clock.hpll_freq) {
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vlv_cck_get(drm);
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/* Obtain SKU information */
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hpll_freq = vlv_cck_read(drm, CCK_FUSE_REG) &
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CCK_FUSE_HPLL_FREQ_MASK;
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vlv_cck_put(drm);
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display->vlv_clock.hpll_freq = vco_freq[hpll_freq] * 1000;
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drm_dbg_kms(drm, "HPLL frequency: %d kHz\n", display->vlv_clock.hpll_freq);
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}
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return display->vlv_clock.hpll_freq;
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}
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static int vlv_clock_get_cck(struct drm_device *drm,
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const char *name, u32 reg, int ref_freq)
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{
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u32 val;
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int divider;
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vlv_cck_get(drm);
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val = vlv_cck_read(drm, reg);
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vlv_cck_put(drm);
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divider = val & CCK_FREQUENCY_VALUES;
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drm_WARN(drm, (val & CCK_FREQUENCY_STATUS) !=
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(divider << CCK_FREQUENCY_STATUS_SHIFT),
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"%s change in progress\n", name);
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return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
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}
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int vlv_clock_get_hrawclk(struct drm_device *drm)
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{
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/* RAWCLK_FREQ_VLV register updated from power well code */
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return vlv_clock_get_cck(drm, "hrawclk", CCK_DISPLAY_REF_CLOCK_CONTROL,
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vlv_clock_get_hpll_vco(drm));
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}
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int vlv_clock_get_czclk(struct drm_device *drm)
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{
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struct intel_display *display = to_intel_display(drm);
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if (!display->vlv_clock.czclk_freq) {
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display->vlv_clock.czclk_freq = vlv_clock_get_cck(drm, "czclk", CCK_CZ_CLOCK_CONTROL,
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vlv_clock_get_hpll_vco(drm));
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drm_dbg_kms(drm, "CZ clock rate: %d kHz\n", display->vlv_clock.czclk_freq);
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}
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return display->vlv_clock.czclk_freq;
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}
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int vlv_clock_get_cdclk(struct drm_device *drm)
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{
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return vlv_clock_get_cck(drm, "cdclk", CCK_DISPLAY_CLOCK_CONTROL,
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vlv_clock_get_hpll_vco(drm));
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}
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int vlv_clock_get_gpll(struct drm_device *drm)
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{
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return vlv_clock_get_cck(drm, "GPLL ref", CCK_GPLL_CLOCK_CONTROL,
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vlv_clock_get_czclk(drm));
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}
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