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796b6df0f8
A DSB buffer which will be used for GOSUB execution does not need the DEWAKE mechanism but still need to be 64 bit aligned. Add helper to finish preparation of a dsb buffer to be executed with GOSUB instruction. v2: Add a cacheline of noops at the end of GOSUB buffer (Ville) Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://lore.kernel.org/r/20250523062041.166468-6-chaitanya.kumar.borah@intel.com
76 lines
2.3 KiB
C
76 lines
2.3 KiB
C
/* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef _INTEL_DSB_H
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#define _INTEL_DSB_H
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#include <linux/types.h>
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#include "i915_reg_defs.h"
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struct intel_atomic_state;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_display;
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struct intel_dsb;
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enum pipe;
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enum intel_dsb_id {
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INTEL_DSB_0,
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INTEL_DSB_1,
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INTEL_DSB_2,
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I915_MAX_DSBS,
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};
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struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state,
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struct intel_crtc *crtc,
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enum intel_dsb_id dsb_id,
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unsigned int max_cmds);
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void intel_dsb_finish(struct intel_dsb *dsb);
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void intel_dsb_gosub_finish(struct intel_dsb *dsb);
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void intel_dsb_cleanup(struct intel_dsb *dsb);
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void intel_dsb_reg_write(struct intel_dsb *dsb,
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i915_reg_t reg, u32 val);
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void intel_dsb_reg_write_indexed(struct intel_dsb *dsb,
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i915_reg_t reg, u32 val);
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void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
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i915_reg_t reg, u32 mask, u32 val);
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void intel_dsb_noop(struct intel_dsb *dsb, int count);
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void intel_dsb_nonpost_start(struct intel_dsb *dsb);
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void intel_dsb_nonpost_end(struct intel_dsb *dsb);
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void intel_dsb_interrupt(struct intel_dsb *dsb);
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void intel_dsb_wait_usec(struct intel_dsb *dsb, int count);
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void intel_dsb_wait_vblanks(struct intel_dsb *dsb, int count);
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void intel_dsb_wait_vblank_delay(struct intel_atomic_state *state,
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struct intel_dsb *dsb);
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void intel_dsb_wait_scanline_in(struct intel_atomic_state *state,
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struct intel_dsb *dsb,
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int lower, int upper);
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void intel_dsb_wait_scanline_out(struct intel_atomic_state *state,
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struct intel_dsb *dsb,
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int lower, int upper);
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void intel_dsb_vblank_evade(struct intel_atomic_state *state,
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struct intel_dsb *dsb);
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void intel_dsb_poll(struct intel_dsb *dsb,
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i915_reg_t reg, u32 mask, u32 val,
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int wait_us, int count);
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void intel_dsb_gosub(struct intel_dsb *dsb,
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struct intel_dsb *sub_dsb);
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void intel_dsb_chain(struct intel_atomic_state *state,
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struct intel_dsb *dsb,
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struct intel_dsb *chained_dsb,
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bool wait_for_vblank);
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void intel_dsb_commit(struct intel_dsb *dsb,
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bool wait_for_vblank);
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void intel_dsb_wait(struct intel_dsb *dsb);
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void intel_dsb_irq_handler(struct intel_display *display,
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enum pipe pipe, enum intel_dsb_id dsb_id);
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#endif
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