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Simple binding with a good description of why the spi-max-frequency is, in practice not as high as the datasheet implies. I've set the maximum as per the value established in the description. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Rob Herring <robh@kernel.org> Cc: Matheus Tavares <matheus.bernardino@usp.br> Cc: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201031184854.745828-2-jic23@kernel.org
61 lines
1.3 KiB
YAML
61 lines
1.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iio/resolver/adi,ad2s90.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Analog Devices AD2S90 Resolver-to-Digital Converter
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maintainers:
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- Matheus Tavares <matheus.bernardino@usp.br>
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description: |
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Datasheet: https://www.analog.com/en/products/ad2s90.html
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properties:
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compatible:
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const: adi,ad2s90
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reg:
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maxItems: 1
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spi-max-frequency:
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maximum: 830000
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description: |
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Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns
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delay is expected between the application of a logic LO to CS and the
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application of SCLK, as also specified. And since the delay is not
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implemented in the spi code, to satisfy it, SCLK's period should be at
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most 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives
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roughly 830000Hz.
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spi-cpol: true
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spi-cpha: true
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additionalProperties: false
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required:
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- compatible
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- reg
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dependencies:
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spi-cpol: [ spi-cpha ]
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spi-cpha: [ spi-cpol ]
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examples:
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- |
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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resolver@0 {
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compatible = "adi,ad2s90";
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reg = <0>;
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spi-max-frequency = <830000>;
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spi-cpol;
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spi-cpha;
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};
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};
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...
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