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cc3c470ae4
Pull ARM driver updates from Arnd Bergmann:
"There are minor updates to SoC specific drivers for chips by Rockchip,
Samsung, NVIDIA, TI, NXP, i.MX, Qualcomm, and Broadcom.
Noteworthy driver changes include:
- Several conversions of DT bindings to yaml format.
- Renesas adds driver support for R-Car V4H, RZ/V2M and RZ/G2UL SoCs.
- Qualcomm adds a bus driver for the SSC (Snapdragon Sensor Core),
and support for more chips in the RPMh power domains and the
soc-id.
- NXP has a new driver for the HDMI blk-ctrl on i.MX8MP.
- Apple M1 gains support for the on-chip NVMe controller, making it
possible to finally use the internal disks. This also includes SoC
drivers for their RTKit IPC and for the SART DMA address filter.
For other subsystems that merge their drivers through the SoC tree, we
have
- Firmware drivers for the ARM firmware stack including TEE, OP-TEE,
SCMI and FF-A get a number of smaller updates and cleanups. OP-TEE
now has a cache for firmware argument structures as an
optimization, and SCMI now supports the 3.1 version of the
specification.
- Reset controller updates to Amlogic, ASpeed, Renesas and ACPI
drivers
- Memory controller updates for Tegra, and a few updates for other
platforms"
* tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (159 commits)
memory: tegra: Add MC error logging on Tegra186 onward
memory: tegra: Add memory controller channels support
memory: tegra: Add APE memory clients for Tegra234
memory: tegra: Add Tegra234 support
nvme-apple: fix sparse endianess warnings
soc/tegra: pmc: Document core domain fields
soc: qcom: pdr: use static for servreg_* variables
soc: imx: fix semicolon.cocci warnings
soc: renesas: R-Car V3U is R-Car Gen4
soc: imx: add i.MX8MP HDMI blk-ctrl
soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
soc: imx: add i.MX8MP HSIO blk-ctrl
soc: imx: imx8m-blk-ctrl: set power device name
soc: qcom: llcc: Add sc8180x and sc8280xp configurations
dt-bindings: arm: msm: Add sc8180x and sc8280xp LLCC compatibles
soc/tegra: pmc: Select REGMAP
dt-bindings: reset: st,sti-powerdown: Convert to yaml
dt-bindings: reset: st,sti-picophyreset: Convert to yaml
dt-bindings: reset: socfpga: Convert to yaml
dt-bindings: reset: snps,axs10x-reset: Convert to yaml
...
132 lines
3.5 KiB
YAML
132 lines
3.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: GENI Serial Engine QUP Wrapper Controller
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description: |
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Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
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is a programmable module for supporting a wide range of serial interfaces
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like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
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Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
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Wrapper controller is modeled as a node with zero or more child nodes each
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representing a serial engine.
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properties:
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compatible:
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enum:
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- qcom,geni-se-qup
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reg:
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description: QUP wrapper common register address and length.
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maxItems: 1
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clock-names:
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items:
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- const: m-ahb
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- const: s-ahb
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clocks:
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items:
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- description: Master AHB Clock
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- description: Slave AHB Clock
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"#address-cells":
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const: 2
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"#size-cells":
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const: 2
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ranges: true
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interconnects:
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maxItems: 1
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interconnect-names:
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const: qup-core
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iommus:
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maxItems: 1
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required:
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- compatible
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- reg
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- clock-names
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- clocks
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- "#address-cells"
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- "#size-cells"
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- ranges
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patternProperties:
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"spi@[0-9a-f]+$":
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type: object
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description: GENI serial engine based SPI controller. SPI in master mode
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supports up to 50MHz, up to four chip selects, programmable
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data path from 4 bits to 32 bits and numerous protocol
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variants.
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$ref: /schemas/spi/qcom,spi-geni-qcom.yaml#
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"i2c@[0-9a-f]+$":
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type: object
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description: GENI serial engine based I2C controller.
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$ref: /schemas/i2c/qcom,i2c-geni-qcom.yaml#
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"serial@[0-9a-f]+$":
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type: object
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description: GENI Serial Engine based UART Controller.
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$ref: /schemas/serial/qcom,serial-geni-qcom.yaml#
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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geniqup@8c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0 0x008c0000 0 0x6000>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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i2c0: i2c@a94000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0xa94000 0 0x4000>;
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interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qup_1_i2c_5_active>;
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pinctrl-1 = <&qup_1_i2c_5_sleep>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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uart0: serial@a88000 {
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compatible = "qcom,geni-uart";
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reg = <0 0xa88000 0 0x7000>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qup_1_uart_3_active>;
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pinctrl-1 = <&qup_1_uart_3_sleep>;
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};
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};
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};
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...
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