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282aa44c21
Pull spi updates from Mark Brown:
"This has mostly been a quiet release for the SPI subsystem, almost all
cleanups and fixes to existing drivers.
A couple of changes that stand out:
- Cleanups and support for version specific features in the
DesignWare controller.
- Removal of support for Netlogic devices from the XLP driver, the
platform had previously been removed by MIPS so the support
couldn't be used.
- Conversion of several DT bindings to YAML format"
* tag 'spi-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (53 commits)
spi: don't include ptp_clock_kernel.h in spi.h
spi: spi-meson-spifc: Add missing pm_runtime_disable() in meson_spifc_probe
spi: atmel: Fix typo
spi: dt-bindings: mediatek,spi-mtk-nor: Fix example 'interrupts' property
spi: qcom: geni: handle timeout for gpi mode
spi: qcom: geni: set the error code for gpi transfer
spi: spi-mux: Add reference to spi-peripheral-props.yaml schema
spi: ar934x: fix transfer size
spi: pxa2xx: Propagate firmware node
spi: dw: Propagate firmware node
spi: dln2: Propagate firmware node
spi: ar934x: fix transfer and word delays
spi: uniphier: Fix a bug that doesn't point to private data correctly
spi: spi-mtk-nor: add new clock name 'axi' for spi nor
spi: atmel,quadspi: Define sama7g5 QSPI
spi: atmel,quadspi: Convert to json-schema
spi: Fix incorrect cs_setup delay handling
dt-bindings: mtd: spi-nor: Add a reference to spi-peripheral-props.yaml
spi: dt-bindings: cdns,qspi-nor: Move peripheral-specific properties out
spi: dt-bindings: add schema listing peripheral-specific properties
...
124 lines
2.6 KiB
YAML
124 lines
2.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cadence Quad SPI controller
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maintainers:
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- Pratyush Yadav <p.yadav@ti.com>
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allOf:
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- $ref: spi-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: xlnx,versal-ospi-1.0
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then:
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required:
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- power-domains
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- ti,k2g-qspi
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- ti,am654-ospi
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- intel,lgm-qspi
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- xlnx,versal-ospi-1.0
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- intel,socfpga-qspi
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- const: cdns,qspi-nor
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- const: cdns,qspi-nor
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reg:
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items:
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- description: the controller register set
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- description: the controller data area
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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cdns,fifo-depth:
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description:
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Size of the data FIFO in words.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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enum: [ 128, 256 ]
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default: 128
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cdns,fifo-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Bus width of the data FIFO in bytes.
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default: 4
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cdns,trigger-address:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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32-bit indirect AHB trigger address.
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cdns,is-decoded-cs:
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type: boolean
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description:
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Flag to indicate whether decoder is used to select different chip select
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for different memory regions.
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cdns,rclk-en:
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type: boolean
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description:
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Flag to indicate that QSPI return clock is used to latch the read
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data rather than the QSPI clock. Make sure that QSPI return clock
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is populated on the board before using this property.
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power-domains:
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maxItems: 1
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resets:
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maxItems: 2
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reset-names:
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minItems: 1
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maxItems: 2
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items:
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enum: [ qspi, qspi-ocp ]
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- cdns,fifo-depth
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- cdns,fifo-width
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- cdns,trigger-address
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- '#address-cells'
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- '#size-cells'
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unevaluatedProperties: false
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examples:
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- |
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qspi: spi@ff705000 {
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compatible = "cdns,qspi-nor";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xff705000 0x1000>,
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<0xffa00000 0x1000>;
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interrupts = <0 151 4>;
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clocks = <&qspi_clk>;
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cdns,fifo-depth = <128>;
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x00000000>;
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resets = <&rst 0x1>, <&rst 0x2>;
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reset-names = "qspi", "qspi-ocp";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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};
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};
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