mirror of
https://github.com/torvalds/linux.git
synced 2026-04-19 07:13:56 -04:00
Pull drm updates from Dave Airlie:
"Highlights:
- Intel xe enable Panthor Lake, started adding WildCat Lake
- amdgpu has a bunch of reset improvments along with the usual IP
updates
- msm got VM_BIND support which is important for vulkan sparse memory
- more drm_panic users
- gpusvm common code to handle a bunch of core SVM work outside
drivers.
Detail summary:
Changes outside drm subdirectory:
- 'shrink_shmem_memory()' for better shmem/hibernate interaction
- Rust support infrastructure:
- make ETIMEDOUT available
- add size constants up to SZ_2G
- add DMA coherent allocation bindings
- mtd driver for Intel GPU non-volatile storage
- i2c designware quirk for Intel xe
core:
- atomic helpers: tune enable/disable sequences
- add task info to wedge API
- refactor EDID quirks
- connector: move HDR sink to drm_display_info
- fourcc: half-float and 32-bit float formats
- mode_config: pass format info to simplify
dma-buf:
- heaps: Give CMA heap a stable name
ci:
- add device tree validation and kunit
displayport:
- change AUX DPCD access probe address
- add quirk for DPCD probe
- add panel replay definitions
- backlight control helpers
fbdev:
- make CONFIG_FIRMWARE_EDID available on all arches
fence:
- fix UAF issues
format-helper:
- improve tests
gpusvm:
- introduce devmem only flag for allocation
- add timeslicing support to GPU SVM
ttm:
- improve eviction
sched:
- tracing improvements
- kunit improvements
- memory leak fixes
- reset handling improvements
color mgmt:
- add hardware gamma LUT handling helpers
bridge:
- add destroy hook
- switch to reference counted drm_bridge allocations
- tc358767: convert to devm_drm_bridge_alloc
- improve CEC handling
panel:
- switch to reference counter drm_panel allocations
- fwnode panel lookup
- Huiling hl055fhv028c support
- Raspberry Pi 7" 720x1280 support
- edp: KDC KD116N3730A05, N160JCE-ELL CMN, N116BCJ-EAK
- simple: AUO P238HAN01
- st7701: Winstar wf40eswaa6mnn0
- visionox: rm69299-shift
- Renesas R61307, Renesas R69328 support
- DJN HX83112B
hdmi:
- add CEC handling
- YUV420 output support
xe:
- WildCat Lake support
- Enable PanthorLake by default
- mark BMG as SRIOV capable
- update firmware recommendations
- Expose media OA units
- aux-bux support for non-volatile memory
- MTD intel-dg driver for non-volatile memory
- Expose fan control and voltage regulator in sysfs
- restructure migration for multi-device
- Restore GuC submit UAF fix
- make GEM shrinker drm managed
- SRIOV VF Post-migration recovery of GGTT nodes
- W/A additions/reworks
- Prefetch support for svm ranges
- Don't allocate managed BO for each policy change
- HWMON fixes for BMG
- Create LRC BO without VM
- PCI ID updates
- make SLPC debugfs files optional
- rework eviction rejection of bound external BOs
- consolidate PAT programming logic for pre/post Xe2
- init changes for flicker-free boot
- Enable GuC Dynamic Inhibit Context switch
i915:
- drm_panic support for i915/xe
- initial flip queue off by default for LNL/PNL
- Wildcat Lake Display support
- Support for DSC fractional link bpp
- Support for simultaneous Panel Replay and Adaptive sync
- Support for PTL+ double buffer LUT
- initial PIPEDMC event handling
- drm_panel_follower support
- DPLL interface renames
- allocate struct intel_display dynamically
- flip queue preperation
- abstract DRAM detection better
- avoid GuC scheduling stalls
- remove DG1 force probe requirement
- fix MEI interrupt handler on RT kernels
- use backlight control helpers for eDP
- more shared display code refactoring
amdgpu:
- add userq slot to INFO ioctl
- SR-IOV hibernation support
- Suspend improvements
- Backlight improvements
- Use scaling for non-native eDP modes
- cleaner shader updates for GC 9.x
- Remove fence slab
- SDMA fw checks for userq support
- RAS updates
- DMCUB updates
- DP tunneling fixes
- Display idle D3 support
- Per queue reset improvements
- initial smartmux support
amdkfd:
- enable KFD on loongarch
- mtype fix for ext coherent system memory
radeon:
- CS validation additional GL extensions
- drop console lock during suspend/resume
- bump driver version
msm:
- VM BIND support
- CI: infrastructure updates
- UBWC single source of truth
- decouple GPU and KMS support
- DP: rework I/O accessors
- DPU: SM8750 support
- DSI: SM8750 support
- GPU: X1-45 support and speedbin support for X1-85
- MDSS: SM8750 support
nova:
- register! macro improvements
- DMA object abstraction
- VBIOS parser + fwsec lookup
- sysmem flush page support
- falcon: generic falcon boot code and HAL
- FWSEC-FRTS: fb setup and load/execute
ivpu:
- Add Wildcat Lake support
- Add turbo flag
ast:
- improve hardware generations implementation
imx:
- IMX8qxq Display Controller support
lima:
- Rockchip RK3528 GPU support
nouveau:
- fence handling cleanup
panfrost:
- MT8370 support
- bo labeling
- 64-bit register access
qaic:
- add RAS support
rockchip:
- convert inno_hdmi to a bridge
rz-du:
- add RZ/V2H(P) support
- MIPI-DSI DCS support
sitronix:
- ST7567 support
sun4i:
- add H616 support
tidss:
- add TI AM62L support
- AM65x OLDI bridge support
bochs:
- drm panic support
vkms:
- YUV and R* format support
- use faux device
vmwgfx:
- fence improvements
hyperv:
- move out of simple
- add drm_panic support"
* tag 'drm-next-2025-07-30' of https://gitlab.freedesktop.org/drm/kernel: (1479 commits)
drm/tidss: oldi: convert to devm_drm_bridge_alloc() API
drm/tidss: encoder: convert to devm_drm_bridge_alloc()
drm/amdgpu: move reset support type checks into the caller
drm/amdgpu/sdma7: re-emit unprocessed state on ring reset
drm/amdgpu/sdma6: re-emit unprocessed state on ring reset
drm/amdgpu/sdma5.2: re-emit unprocessed state on ring reset
drm/amdgpu/sdma5: re-emit unprocessed state on ring reset
drm/amdgpu/gfx12: re-emit unprocessed state on ring reset
drm/amdgpu/gfx11: re-emit unprocessed state on ring reset
drm/amdgpu/gfx10: re-emit unprocessed state on ring reset
drm/amdgpu/gfx9.4.3: re-emit unprocessed state on kcq reset
drm/amdgpu/gfx9: re-emit unprocessed state on kcq reset
drm/amdgpu: Add WARN_ON to the resource clear function
drm/amd/pm: Use cached metrics data on SMUv13.0.6
drm/amd/pm: Use cached data for min/max clocks
gpu: nova-core: fix bounds check in PmuLookupTableEntry::new
drm/amdgpu: Replace HQD terminology with slots naming
drm/amdgpu: Add user queue instance count in HW IP info
drm/amd/amdgpu: Add helper functions for isp buffers
drm/amd/amdgpu: Initialize swnode for ISP MFD device
...
226 lines
4.8 KiB
C
226 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
|
||
/* Copyright © 2024 Intel Corporation */
|
||
#include <linux/bitfield.h>
|
||
#include <linux/bits.h>
|
||
#include <linux/cleanup.h>
|
||
#include <linux/errno.h>
|
||
#include <linux/intel_vsec.h>
|
||
#include <linux/module.h>
|
||
#include <linux/mutex.h>
|
||
#include <linux/pci.h>
|
||
#include <linux/types.h>
|
||
|
||
#include "xe_device.h"
|
||
#include "xe_device_types.h"
|
||
#include "xe_drv.h"
|
||
#include "xe_mmio.h"
|
||
#include "xe_platform_types.h"
|
||
#include "xe_pm.h"
|
||
#include "xe_vsec.h"
|
||
|
||
#include "regs/xe_pmt.h"
|
||
|
||
/* PMT GUID value for BMG devices. NOTE: this is NOT a PCI id */
|
||
#define BMG_DEVICE_ID 0xE2F8
|
||
|
||
static struct intel_vsec_header bmg_telemetry = {
|
||
.rev = 1,
|
||
.length = 0x10,
|
||
.id = VSEC_ID_TELEMETRY,
|
||
.num_entries = 2,
|
||
.entry_size = 4,
|
||
.tbir = 0,
|
||
.offset = BMG_DISCOVERY_OFFSET,
|
||
};
|
||
|
||
static struct intel_vsec_header bmg_crashlog = {
|
||
.rev = 1,
|
||
.length = 0x10,
|
||
.id = VSEC_ID_CRASHLOG,
|
||
.num_entries = 2,
|
||
.entry_size = 6,
|
||
.tbir = 0,
|
||
.offset = BMG_DISCOVERY_OFFSET + 0x60,
|
||
};
|
||
|
||
static struct intel_vsec_header *bmg_capabilities[] = {
|
||
&bmg_telemetry,
|
||
&bmg_crashlog,
|
||
NULL
|
||
};
|
||
|
||
enum xe_vsec {
|
||
XE_VSEC_UNKNOWN = 0,
|
||
XE_VSEC_BMG,
|
||
};
|
||
|
||
static struct intel_vsec_platform_info xe_vsec_info[] = {
|
||
[XE_VSEC_BMG] = {
|
||
.caps = VSEC_CAP_TELEMETRY | VSEC_CAP_CRASHLOG,
|
||
.headers = bmg_capabilities,
|
||
},
|
||
{ }
|
||
};
|
||
|
||
/*
|
||
* The GUID will have the following bits to decode:
|
||
* [0:3] - {Telemetry space iteration number (0,1,..)}
|
||
* [4:7] - Segment (SEGMENT_INDEPENDENT-0, Client-1, Server-2)
|
||
* [8:11] - SOC_SKU
|
||
* [12:27] – Device ID – changes for each down bin SKU’s
|
||
* [28:29] - Capability Type (Crashlog-0, Telemetry Aggregator-1, Watcher-2)
|
||
* [30:31] - Record-ID (0-PUNIT, 1-OOBMSM_0, 2-OOBMSM_1)
|
||
*/
|
||
#define GUID_TELEM_ITERATION GENMASK(3, 0)
|
||
#define GUID_SEGMENT GENMASK(7, 4)
|
||
#define GUID_SOC_SKU GENMASK(11, 8)
|
||
#define GUID_DEVICE_ID GENMASK(27, 12)
|
||
#define GUID_CAP_TYPE GENMASK(29, 28)
|
||
#define GUID_RECORD_ID GENMASK(31, 30)
|
||
|
||
#define PUNIT_TELEMETRY_OFFSET 0x0200
|
||
#define PUNIT_WATCHER_OFFSET 0x14A0
|
||
#define OOBMSM_0_WATCHER_OFFSET 0x18D8
|
||
#define OOBMSM_1_TELEMETRY_OFFSET 0x1000
|
||
|
||
enum record_id {
|
||
PUNIT,
|
||
OOBMSM_0,
|
||
OOBMSM_1,
|
||
};
|
||
|
||
enum capability {
|
||
CRASHLOG,
|
||
TELEMETRY,
|
||
WATCHER,
|
||
};
|
||
|
||
static int xe_guid_decode(u32 guid, int *index, u32 *offset)
|
||
{
|
||
u32 record_id = FIELD_GET(GUID_RECORD_ID, guid);
|
||
u32 cap_type = FIELD_GET(GUID_CAP_TYPE, guid);
|
||
u32 device_id = FIELD_GET(GUID_DEVICE_ID, guid);
|
||
|
||
if (device_id != BMG_DEVICE_ID)
|
||
return -ENODEV;
|
||
|
||
if (cap_type > WATCHER)
|
||
return -EINVAL;
|
||
|
||
*offset = 0;
|
||
|
||
if (cap_type == CRASHLOG) {
|
||
*index = record_id == PUNIT ? 2 : 4;
|
||
return 0;
|
||
}
|
||
|
||
switch (record_id) {
|
||
case PUNIT:
|
||
*index = 0;
|
||
if (cap_type == TELEMETRY)
|
||
*offset = PUNIT_TELEMETRY_OFFSET;
|
||
else
|
||
*offset = PUNIT_WATCHER_OFFSET;
|
||
break;
|
||
|
||
case OOBMSM_0:
|
||
*index = 1;
|
||
if (cap_type == WATCHER)
|
||
*offset = OOBMSM_0_WATCHER_OFFSET;
|
||
break;
|
||
|
||
case OOBMSM_1:
|
||
*index = 1;
|
||
if (cap_type == TELEMETRY)
|
||
*offset = OOBMSM_1_TELEMETRY_OFFSET;
|
||
break;
|
||
default:
|
||
return -EINVAL;
|
||
}
|
||
|
||
return 0;
|
||
}
|
||
|
||
int xe_pmt_telem_read(struct pci_dev *pdev, u32 guid, u64 *data, loff_t user_offset,
|
||
u32 count)
|
||
{
|
||
struct xe_device *xe = pdev_to_xe_device(pdev);
|
||
void __iomem *telem_addr = xe->mmio.regs + BMG_TELEMETRY_OFFSET;
|
||
u32 mem_region;
|
||
u32 offset;
|
||
int ret;
|
||
|
||
ret = xe_guid_decode(guid, &mem_region, &offset);
|
||
if (ret)
|
||
return ret;
|
||
|
||
telem_addr += offset + user_offset;
|
||
|
||
guard(mutex)(&xe->pmt.lock);
|
||
|
||
/* indicate that we are not at an appropriate power level */
|
||
if (!xe_pm_runtime_get_if_active(xe))
|
||
return -ENODATA;
|
||
|
||
/* set SoC re-mapper index register based on GUID memory region */
|
||
xe_mmio_rmw32(xe_root_tile_mmio(xe), SG_REMAP_INDEX1, SG_REMAP_BITS,
|
||
REG_FIELD_PREP(SG_REMAP_BITS, mem_region));
|
||
|
||
memcpy_fromio(data, telem_addr, count);
|
||
xe_pm_runtime_put(xe);
|
||
|
||
return count;
|
||
}
|
||
|
||
static struct pmt_callbacks xe_pmt_cb = {
|
||
.read_telem = xe_pmt_telem_read,
|
||
};
|
||
|
||
static const int vsec_platforms[] = {
|
||
[XE_BATTLEMAGE] = XE_VSEC_BMG,
|
||
};
|
||
|
||
static enum xe_vsec get_platform_info(struct xe_device *xe)
|
||
{
|
||
if (xe->info.platform > XE_BATTLEMAGE)
|
||
return XE_VSEC_UNKNOWN;
|
||
|
||
return vsec_platforms[xe->info.platform];
|
||
}
|
||
|
||
/**
|
||
* xe_vsec_init - Initialize resources and add intel_vsec auxiliary
|
||
* interface
|
||
* @xe: valid xe instance
|
||
*/
|
||
void xe_vsec_init(struct xe_device *xe)
|
||
{
|
||
struct intel_vsec_platform_info *info;
|
||
struct device *dev = xe->drm.dev;
|
||
struct pci_dev *pdev = to_pci_dev(dev);
|
||
enum xe_vsec platform;
|
||
|
||
platform = get_platform_info(xe);
|
||
if (platform == XE_VSEC_UNKNOWN)
|
||
return;
|
||
|
||
info = &xe_vsec_info[platform];
|
||
if (!info->headers)
|
||
return;
|
||
|
||
switch (platform) {
|
||
case XE_VSEC_BMG:
|
||
info->priv_data = &xe_pmt_cb;
|
||
break;
|
||
default:
|
||
break;
|
||
}
|
||
|
||
/*
|
||
* Register a VSEC. Cleanup is handled using device managed
|
||
* resources.
|
||
*/
|
||
intel_vsec_register(pdev, info);
|
||
}
|
||
MODULE_IMPORT_NS("INTEL_VSEC");
|