mirror of
https://github.com/torvalds/linux.git
synced 2026-04-28 19:42:31 -04:00
9b6d351a75
Pull ARM SoC DT updates from Olof Johansson:
"DT and DT-conversion-related changes for various ARM platforms. Most
of these are to enable various devices on various boards, etc, and not
necessarily worth enumerating.
New boards and systems continue to come in as new devicetree files
that don't require corresponding C changes any more, which is
indicating that the system is starting to work fairly well.
A few things worth pointing out:
* ST Ericsson ux500 platforms have made the major push to move over
to fully support the platform with DT
* Renesas platforms continue their conversion over from legacy
platform devices to DT-based for hardware description"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (327 commits)
ARM: dts: SiRF: add pin group for USP0 with only RX or TX frame sync
ARM: dts: SiRF: add lost usp1_uart_nostreamctrl pin group for atlas6
ARM: dts: sirf: add lost minigpsrtc device node
ARM: dts: sirf: add clock, frequence-voltage table for CPU0
ARM: dts: sirf: add lost bus_width, clock and status for sdhci
ARM: dts: sirf: add lost clocks for cphifbg
ARM: dts: socfpga: add pl330 clock
ARM: dts: socfpga: update L2 tag and data latency
arm: sun7i: cubietruck: Enable the i2c controllers
ARM: dts: add support for EXYNOS4412 based TINY4412 board
ARM: dts: Add initial support for Arndale Octa board
ARM: bcm2835: add USB controller to device tree
ARM: dts: MSM8974: Add MMIO architected timer node
ARM: dts: MSM8974: Add restart node
ARM: dts: sun7i: external clock outputs
ARM: dts: sun7i: Change 32768 Hz oscillator node name to clk@N style
ARM: dts: sun7i: Add pin muxing options for clock outputs
ARM: dts: sun7i: Add rtp controller node
ARM: dts: sun5i: Add rtp controller node
ARM: dts: sun4i: Add rtp controller node
...
108 lines
3.1 KiB
Plaintext
108 lines
3.1 KiB
Plaintext
Atmel AT91 device tree bindings.
|
|
================================
|
|
|
|
PIT Timer required properties:
|
|
- compatible: Should be "atmel,at91sam9260-pit"
|
|
- reg: Should contain registers location and length
|
|
- interrupts: Should contain interrupt for the PIT which is the IRQ line
|
|
shared across all System Controller members.
|
|
|
|
System Timer (ST) required properties:
|
|
- compatible: Should be "atmel,at91rm9200-st"
|
|
- reg: Should contain registers location and length
|
|
- interrupts: Should contain interrupt for the ST which is the IRQ line
|
|
shared across all System Controller members.
|
|
|
|
TC/TCLIB Timer required properties:
|
|
- compatible: Should be "atmel,<chip>-tcb".
|
|
<chip> can be "at91rm9200" or "at91sam9x5"
|
|
- reg: Should contain registers location and length
|
|
- interrupts: Should contain all interrupts for the TC block
|
|
Note that you can specify several interrupt cells if the TC
|
|
block has one interrupt per channel.
|
|
- clock-names: tuple listing input clock names.
|
|
Required elements: "t0_clk"
|
|
Optional elements: "t1_clk", "t2_clk"
|
|
- clocks: phandles to input clocks.
|
|
|
|
Examples:
|
|
|
|
One interrupt per TC block:
|
|
tcb0: timer@fff7c000 {
|
|
compatible = "atmel,at91rm9200-tcb";
|
|
reg = <0xfff7c000 0x100>;
|
|
interrupts = <18 4>;
|
|
clocks = <&tcb0_clk>;
|
|
clock-names = "t0_clk";
|
|
};
|
|
|
|
One interrupt per TC channel in a TC block:
|
|
tcb1: timer@fffdc000 {
|
|
compatible = "atmel,at91rm9200-tcb";
|
|
reg = <0xfffdc000 0x100>;
|
|
interrupts = <26 4 27 4 28 4>;
|
|
clocks = <&tcb1_clk>;
|
|
clock-names = "t0_clk";
|
|
};
|
|
|
|
RSTC Reset Controller required properties:
|
|
- compatible: Should be "atmel,<chip>-rstc".
|
|
<chip> can be "at91sam9260" or "at91sam9g45"
|
|
- reg: Should contain registers location and length
|
|
|
|
Example:
|
|
|
|
rstc@fffffd00 {
|
|
compatible = "atmel,at91sam9260-rstc";
|
|
reg = <0xfffffd00 0x10>;
|
|
};
|
|
|
|
RAMC SDRAM/DDR Controller required properties:
|
|
- compatible: Should be "atmel,at91rm9200-sdramc",
|
|
"atmel,at91sam9260-sdramc",
|
|
"atmel,at91sam9g45-ddramc",
|
|
- reg: Should contain registers location and length
|
|
For at91sam9263 and at91sam9g45 you must specify 2 entries.
|
|
|
|
Examples:
|
|
|
|
ramc0: ramc@ffffe800 {
|
|
compatible = "atmel,at91sam9g45-ddramc";
|
|
reg = <0xffffe800 0x200>;
|
|
};
|
|
|
|
ramc0: ramc@ffffe400 {
|
|
compatible = "atmel,at91sam9g45-ddramc";
|
|
reg = <0xffffe400 0x200
|
|
0xffffe600 0x200>;
|
|
};
|
|
|
|
SHDWC Shutdown Controller
|
|
|
|
required properties:
|
|
- compatible: Should be "atmel,<chip>-shdwc".
|
|
<chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
|
|
- reg: Should contain registers location and length
|
|
|
|
optional properties:
|
|
- atmel,wakeup-mode: String, operation mode of the wakeup mode.
|
|
Supported values are: "none", "high", "low", "any".
|
|
- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
|
|
|
|
optional at91sam9260 properties:
|
|
- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
|
|
|
|
optional at91sam9rl properties:
|
|
- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
|
|
- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
|
|
|
|
optional at91sam9x5 properties:
|
|
- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
|
|
|
|
Example:
|
|
|
|
rstc@fffffd00 {
|
|
compatible = "atmel,at91sam9260-rstc";
|
|
reg = <0xfffffd00 0x10>;
|
|
};
|