mirror of
https://github.com/torvalds/linux.git
synced 2026-04-30 20:42:33 -04:00
d4e1f5a14e
Pull ARM SoC device-tree changes from Olof Johansson:
"Unlike the board branch, this keeps having large sets of changes for
every release, but that's quite expected and is so far working well.
Most of this is plumbing for various device bindings and new
platforms, but there's also a bit of cleanup and code removal for
things that are moved from platform code to DT contents (some OMAP
clock code in particular).
There's also a pinctrl driver for tegra here (appropriately acked),
that's introduced this way to make it more bisectable.
I'm happy to say that there were no conflicts at all with this branch
this release, which means that changes are flowing through our tree as
expected instead of merged through driver maintainers (or at least not
done with conflicts).
There are several new boards added, and a couple of SoCs. In no
particular order:
- Rockchip RK3288 SoC support, including DTS for a dev board that
they have seeded with some community developers.
- Better support for Hardkernel Exynos4-based ODROID boards.
- CCF conversions (and dtsi contents) for several Renesas platforms.
- Gumstix Pepper (TI AM335x) board support
- TI eval board support for AM437x
- Allwinner A23 SoC, very similar to existing ones which mostly has
resulted in DT changes for support. Also includes support for an
Ippo tablet with the chipset.
- Allwinner A31 Hummingbird board support, not to be confused with
the SolidRun i.MX-based Hummingboard.
- Tegra30 Apalis board support"
* tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (334 commits)
ARM: dts: Enable USB host0 (EHCI) on rk3288-evb
ARM: dts: add rk3288 ehci usb devices
ARM: dts: Turn on USB host vbus on rk3288-evb
ARM: tegra: apalis t30: fix device tree compatible node
ARM: tegra: paz00: Fix some indentation inconsistencies
ARM: zynq: DT: Clarify Xilinx Zynq platform
ARM: dts: rockchip: add watchdog node
ARM: dts: rockchip: remove pinctrl setting from radxarock uart2
ARM: dts: Add missing pinctrl for uart0/1 for exynos3250
ARM: dts: Remove duplicate 'interrput-parent' property for exynos3250
ARM: dts: Add TMU dt node to monitor the temperature for exynos3250
ARM: dts: Specify MAX77686 pmic interrupt for exynos5250-smdk5250
ARM: dts: cypress,cyapa trackpad is exynos5250-Snow only
ARM: dts: max77686 is exynos5250-snow only
ARM: zynq: DT: Remove DMA from board DTs
ARM: zynq: DT: Add CAN node
ARM: EXYNOS: Add exynos5260 PMU compatible string to DT match table
ARM: dts: Add PMU DT node for exynos5260 SoC
ARM: EXYNOS: Add support for Exynos5410 PMU
ARM: dts: Add PMU to exynos5410
...
489 lines
12 KiB
Plaintext
489 lines
12 KiB
Plaintext
/*
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* Device Tree Source for Renesas r8a7779
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Simon Horman
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/r8a7779-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "renesas,r8a7779";
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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clock-frequency = <1000000000>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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clock-frequency = <1000000000>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <2>;
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clock-frequency = <1000000000>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <3>;
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clock-frequency = <1000000000>;
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};
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};
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aliases {
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spi0 = &hspi0;
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spi1 = &hspi1;
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spi2 = &hspi2;
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};
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gic: interrupt-controller@f0001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xf0001000 0x1000>,
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<0xf0000100 0x100>;
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};
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gpio0: gpio@ffc40000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc40000 0x2c>;
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interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio1: gpio@ffc41000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc41000 0x2c>;
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interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio2: gpio@ffc42000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc42000 0x2c>;
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interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio3: gpio@ffc43000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc43000 0x2c>;
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interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio4: gpio@ffc44000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc44000 0x2c>;
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interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio5: gpio@ffc45000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc45000 0x2c>;
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interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio6: gpio@ffc46000 {
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compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
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reg = <0xffc46000 0x2c>;
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interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 192 9>;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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irqpin0: irqpin@fe780010 {
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compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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status = "disabled";
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interrupt-controller;
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reg = <0xfe78001c 4>,
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<0xfe780010 4>,
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<0xfe780024 4>,
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<0xfe780044 4>,
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<0xfe780064 4>;
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interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
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0 28 IRQ_TYPE_LEVEL_HIGH
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0 29 IRQ_TYPE_LEVEL_HIGH
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0 30 IRQ_TYPE_LEVEL_HIGH>;
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sense-bitfield-width = <2>;
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};
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i2c0: i2c@ffc70000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7779";
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reg = <0xffc70000 0x1000>;
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interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
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status = "disabled";
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};
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i2c1: i2c@ffc71000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7779";
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reg = <0xffc71000 0x1000>;
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interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
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status = "disabled";
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};
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i2c2: i2c@ffc72000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7779";
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reg = <0xffc72000 0x1000>;
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interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
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status = "disabled";
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};
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i2c3: i2c@ffc73000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7779";
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reg = <0xffc73000 0x1000>;
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interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
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status = "disabled";
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};
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scif0: serial@ffe40000 {
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe40000 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scif1: serial@ffe41000 {
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe41000 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scif2: serial@ffe42000 {
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe42000 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scif3: serial@ffe43000 {
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe43000 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scif4: serial@ffe44000 {
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe44000 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scif5: serial@ffe45000 {
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compatible = "renesas,scif-r8a7779", "renesas,scif";
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reg = <0xffe45000 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg_clocks R8A7779_CLK_P>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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pfc: pfc@fffc0000 {
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compatible = "renesas,pfc-r8a7779";
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reg = <0xfffc0000 0x23c>;
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};
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thermal@ffc48000 {
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compatible = "renesas,rcar-thermal";
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reg = <0xffc48000 0x38>;
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};
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sata: sata@fc600000 {
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compatible = "renesas,rcar-sata";
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reg = <0xfc600000 0x2000>;
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interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7779_CLK_SATA>;
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};
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sdhi0: sd@ffe4c000 {
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compatible = "renesas,sdhi-r8a7779";
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reg = <0xffe4c000 0x100>;
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interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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};
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sdhi1: sd@ffe4d000 {
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compatible = "renesas,sdhi-r8a7779";
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reg = <0xffe4d000 0x100>;
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interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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};
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sdhi2: sd@ffe4e000 {
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compatible = "renesas,sdhi-r8a7779";
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reg = <0xffe4e000 0x100>;
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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};
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sdhi3: sd@ffe4f000 {
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compatible = "renesas,sdhi-r8a7779";
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reg = <0xffe4f000 0x100>;
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interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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};
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hspi0: spi@fffc7000 {
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compatible = "renesas,hspi-r8a7779", "renesas,hspi";
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reg = <0xfffc7000 0x18>;
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interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
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status = "disabled";
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};
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hspi1: spi@fffc8000 {
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compatible = "renesas,hspi-r8a7779", "renesas,hspi";
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reg = <0xfffc8000 0x18>;
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interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
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status = "disabled";
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};
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hspi2: spi@fffc6000 {
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compatible = "renesas,hspi-r8a7779", "renesas,hspi";
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reg = <0xfffc6000 0x18>;
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interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
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status = "disabled";
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* External root clock */
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extal_clk: extal_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overriden by the board. */
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clock-frequency = <0>;
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clock-output-names = "extal";
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};
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/* Special CPG clocks */
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cpg_clocks: clocks@ffc80000 {
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compatible = "renesas,r8a7779-cpg-clocks";
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reg = <0xffc80000 0x30>;
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clocks = <&extal_clk>;
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#clock-cells = <1>;
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clock-output-names = "plla", "z", "zs", "s",
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"s1", "p", "b", "out";
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};
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/* Fixed factor clocks */
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i_clk: i_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "i";
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};
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s3_clk: s3_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
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#clock-cells = <0>;
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clock-div = <8>;
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clock-mult = <1>;
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clock-output-names = "s3";
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};
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s4_clk: s4_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
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#clock-cells = <0>;
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clock-div = <16>;
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clock-mult = <1>;
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clock-output-names = "s4";
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};
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g_clk: g_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
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#clock-cells = <0>;
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clock-div = <24>;
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clock-mult = <1>;
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clock-output-names = "g";
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};
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/* Gate clocks */
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mstp0_clks: clocks@ffc80030 {
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compatible = "renesas,r8a7779-mstp-clocks",
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"renesas,cpg-mstp-clocks";
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reg = <0xffc80030 4>;
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clocks = <&cpg_clocks R8A7779_CLK_S>,
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<&cpg_clocks R8A7779_CLK_P>,
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<&cpg_clocks R8A7779_CLK_P>,
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<&cpg_clocks R8A7779_CLK_P>,
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<&cpg_clocks R8A7779_CLK_S>,
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<&cpg_clocks R8A7779_CLK_S>,
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<&cpg_clocks R8A7779_CLK_S1>,
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<&cpg_clocks R8A7779_CLK_S1>,
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<&cpg_clocks R8A7779_CLK_S1>,
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<&cpg_clocks R8A7779_CLK_S1>,
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<&cpg_clocks R8A7779_CLK_S1>,
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<&cpg_clocks R8A7779_CLK_S1>,
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<&cpg_clocks R8A7779_CLK_P>,
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<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7779_CLK_HSPI R8A7779_CLK_TMU2
|
|
R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
|
|
R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
|
|
R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
|
|
R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
|
|
R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
|
|
R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
|
|
R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
|
|
>;
|
|
clock-output-names =
|
|
"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
|
|
"hscif0", "scif5", "scif4", "scif3", "scif2",
|
|
"scif1", "scif0", "i2c3", "i2c2", "i2c1",
|
|
"i2c0";
|
|
};
|
|
mstp1_clks: clocks@ffc80034 {
|
|
compatible = "renesas,r8a7779-mstp-clocks",
|
|
"renesas,cpg-mstp-clocks";
|
|
reg = <0xffc80034 4>, <0xffc80044 4>;
|
|
clocks = <&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_S>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_P>,
|
|
<&cpg_clocks R8A7779_CLK_S>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7779_CLK_USB01 R8A7779_CLK_USB2
|
|
R8A7779_CLK_DU R8A7779_CLK_VIN2
|
|
R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
|
|
R8A7779_CLK_ETHER R8A7779_CLK_SATA
|
|
R8A7779_CLK_PCIE R8A7779_CLK_VIN3
|
|
>;
|
|
clock-output-names =
|
|
"usb01", "usb2",
|
|
"du", "vin2",
|
|
"vin1", "vin0",
|
|
"ether", "sata",
|
|
"pcie", "vin3";
|
|
};
|
|
mstp3_clks: clocks@ffc8003c {
|
|
compatible = "renesas,r8a7779-mstp-clocks",
|
|
"renesas,cpg-mstp-clocks";
|
|
reg = <0xffc8003c 4>;
|
|
clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
|
|
<&s4_clk>, <&s4_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
|
|
R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
|
|
R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
|
|
>;
|
|
clock-output-names =
|
|
"sdhi3", "sdhi2", "sdhi1", "sdhi0",
|
|
"mmc1", "mmc0";
|
|
};
|
|
};
|
|
};
|