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The display IPs in MediaTek SoCs support being interconnected with different instances of DDP IPs (for example, merge0 or merge1) and/or with different DDP IPs (for example, rdma can be connected with either color, dpi, dsi, merge, etc), forming a full Display Data Path that ends with an actual display. The final display pipeline is effectively board specific, as it does depend on the display that is attached to it, and eventually on the sensors supported by the board (for example, Adaptive Ambient Light would need an Ambient Light Sensor, otherwise it's pointless!), other than the output type. Add support for OF graphs to most of the MediaTek DDP (display) bindings to add flexibility to build custom hardware paths, hence enabling board specific configuration of the display pipeline and allowing to finally migrate away from using hardcoded paths. Please note that - while this commit retains retro-compatibility with old device trees - it will break the ABI for mediatek,dsi and for mediatek,dpi for the sake of consistency between the `ports` in all MediaTek DRM drivers versus DRM bridge drivers as in the previous binding, MediaTek was using `port` (implicitly, port@0) as an OUTPUT, while now the first port is an INPUT, and the second one is an OUTPUT, which is consistent with other DRM drivers which can be chained to drm/mediatek. As for maintainability concerns, I am aware that the old device tree will not be actively tested anymore, but retrocompatibility breakages will *not* be more likely to happen in the future because any addition to the graph (new drivers) will be done only for features present on newer SoCs, keeping the old ones (and their default pipeline) untouched. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Tested-by: Michael Walle <mwalle@kernel.org> # on kontron-sbc-i1200 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patchwork.kernel.org/project/dri-devel/patch/20241017103809.156056-2-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
105 lines
3.0 KiB
YAML
105 lines
3.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: mediatek display DSC controller
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maintainers:
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- Chun-Kuang Hu <chunkuang.hu@kernel.org>
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- Philipp Zabel <p.zabel@pengutronix.de>
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description: |
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The DSC standard is a specification of the algorithms used for
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compressing and decompressing image display streams, including
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the specification of the syntax and semantics of the compressed
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video bit stream. DSC is designed for real-time systems with
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real-time compression, transmission, decompression and Display.
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properties:
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compatible:
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oneOf:
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- enum:
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- mediatek,mt8195-disp-dsc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: DSC Wrapper Clock
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power-domains:
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description: A phandle and PM domain specifier as defined by bindings of
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the power controller specified by phandle. See
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Documentation/devicetree/bindings/power/power-domain.yaml for details.
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mediatek,gce-client-reg:
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description:
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The register of client driver can be configured by gce with 4 arguments
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defined in this property, such as phandle of gce, subsys id,
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register offset and size.
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Each subsys id is mapping to a base address of display function blocks
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register which is defined in the gce header
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include/dt-bindings/gce/<chip>-gce.h.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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Input and output ports can have multiple endpoints, each of those
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connects to either the primary, secondary, etc, display pipeline.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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Display Stream Compression input, usually from one of the DITHER
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or MERGE blocks.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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Display Stream Compression output to the input of the next desired
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component in the display pipeline, for example to MERGE, DP_INTF,
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DPI or DSI.
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- interrupts
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- power-domains
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt8195-clk.h>
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#include <dt-bindings/power/mt8195-power.h>
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#include <dt-bindings/gce/mt8195-gce.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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dsc0: disp_dsc_wrap@1c009000 {
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compatible = "mediatek,mt8195-disp-dsc";
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reg = <0 0x1c009000 0 0x1000>;
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interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
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clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
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mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
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};
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};
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