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342d482105
Split of the bindings was artificial and not helping - we end up with multiple binding files for very similar devices thus increasing the chances of using different order of reg and clocks entries. Unify DPU bindings of SC7280 and SM8550, because they are the same. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/617874/ Link: https://lore.kernel.org/r/20241003-dt-binding-display-msm-merge-v1-5-91ab08fc76a2@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
114 lines
2.7 KiB
YAML
114 lines
2.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-dpu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display DPU on SC7280
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Neil Armstrong <neil.armstrong@linaro.org>
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- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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- Krishna Manikandan <quic_mkrishn@quicinc.com>
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$ref: /schemas/display/msm/dpu-common.yaml#
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properties:
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compatible:
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enum:
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- qcom,sc7280-dpu
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- qcom,sc8280xp-dpu
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- qcom,sm8350-dpu
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- qcom,sm8450-dpu
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- qcom,sm8550-dpu
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reg:
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items:
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- description: Address offset and size for mdp register set
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- description: Address offset and size for vbif register set
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reg-names:
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items:
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- const: mdp
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- const: vbif
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clocks:
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items:
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- description: Display hf axi clock
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- description: Display sf axi clock
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- description: Display ahb clock
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- description: Display lut clock
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- description: Display core clock
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- description: Display vsync clock
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clock-names:
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items:
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- const: bus
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- const: nrt_bus
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- const: iface
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- const: lut
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- const: core
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- const: vsync
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
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#include <dt-bindings/clock/qcom,gcc-sc7280.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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display-controller@ae01000 {
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compatible = "qcom,sc7280-dpu";
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reg = <0x0ae01000 0x8f000>,
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<0x0aeb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
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<&gcc GCC_DISP_SF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "bus",
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"nrt_bus",
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"iface",
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"lut",
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"core",
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"vsync";
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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power-domains = <&rpmhpd SC7280_CX>;
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operating-points-v2 = <&mdp_opp_table>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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port@1 {
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reg = <1>;
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endpoint {
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remote-endpoint = <&edp_in>;
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};
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};
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};
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};
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...
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