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The UART of SG2044 is modified version of the standard Synopsys DesignWare UART. The UART on SG2044 relys on the internal divisor and can not set right clock rate for the common bitrates. Add compatibles string for the Sophgo SG2044 uarts. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241024062105.782330-3-inochiama@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
175 lines
4.1 KiB
YAML
175 lines
4.1 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DesignWare ABP UART
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maintainers:
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- Rob Herring <robh@kernel.org>
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allOf:
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- $ref: serial.yaml#
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- $ref: rs485.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: starfive,jh7110-uart
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then:
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properties:
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resets:
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minItems: 2
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else:
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properties:
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resets:
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maxItems: 1
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- renesas,r9a06g032-uart
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- renesas,r9a06g033-uart
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- const: renesas,rzn1-uart
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- items:
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- enum:
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- brcm,bcm11351-dw-apb-uart
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- brcm,bcm21664-dw-apb-uart
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- rockchip,px30-uart
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- rockchip,rk1808-uart
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- rockchip,rk3036-uart
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- rockchip,rk3066-uart
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- rockchip,rk3128-uart
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- rockchip,rk3188-uart
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- rockchip,rk3288-uart
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- rockchip,rk3308-uart
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- rockchip,rk3328-uart
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- rockchip,rk3368-uart
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- rockchip,rk3399-uart
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- rockchip,rk3528-uart
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- rockchip,rk3568-uart
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- rockchip,rk3576-uart
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- rockchip,rk3588-uart
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- rockchip,rv1108-uart
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- rockchip,rv1126-uart
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- sophgo,sg2044-uart
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- starfive,jh7100-hsuart
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- starfive,jh7100-uart
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- starfive,jh7110-uart
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- const: snps,dw-apb-uart
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- const: snps,dw-apb-uart
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clock-frequency: true
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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items:
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- const: baudclk
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- const: apb_pclk
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dmas:
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maxItems: 2
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dma-names:
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items:
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- const: tx
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- const: rx
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snps,uart-16550-compatible:
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description: reflects the value of UART_16550_COMPATIBLE configuration
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parameter. Define this if your UART does not implement the busy functionality.
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type: boolean
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resets:
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minItems: 1
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maxItems: 2
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reg-shift: true
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reg-io-width: true
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dcd-override:
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description: Override the DCD modem status signal. This signal will
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always be reported as active instead of being obtained from the modem
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status register. Define this if your serial port does not use this
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pin.
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type: boolean
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dsr-override:
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description: Override the DTS modem status signal. This signal will
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always be reported as active instead of being obtained from the modem
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status register. Define this if your serial port does not use this
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pin.
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type: boolean
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cts-override:
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description: Override the CTS modem status signal. This signal will
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always be reported as active instead of being obtained from the modem
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status register. Define this if your serial port does not use this
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pin.
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type: boolean
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ri-override:
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description: Override the RI modem status signal. This signal will always
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be reported as inactive instead of being obtained from the modem status
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register. Define this if your serial port does not use this pin.
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type: boolean
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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serial@80230000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x80230000 0x100>;
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clock-frequency = <3686400>;
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interrupts = <10>;
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reg-shift = <2>;
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reg-io-width = <4>;
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dcd-override;
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dsr-override;
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cts-override;
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ri-override;
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};
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- |
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// Example with one clock:
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serial@80230000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x80230000 0x100>;
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clocks = <&baudclk>;
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interrupts = <10>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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- |
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// Example with two clocks:
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serial@80230000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x80230000 0x100>;
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clocks = <&baudclk>, <&apb_pclk>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <10>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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...
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