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759541d78e
Linear mode is only supported by the Zynq UltraScale QSPI controller, so update the bindings to include two 'reg' properties only for the Zynq UltraScale QSPI controller. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://patch.msgid.link/20240925114203.2234735-1-amit.kumar-mahapatra@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
83 lines
1.4 KiB
YAML
83 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
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maintainers:
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- Michal Simek <michal.simek@amd.com>
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properties:
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compatible:
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enum:
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- xlnx,versal-qspi-1.0
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- xlnx,zynqmp-qspi-1.0
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reg:
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minItems: 1
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maxItems: 2
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interrupts:
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maxItems: 1
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clock-names:
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items:
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- const: ref_clk
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- const: pclk
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clocks:
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maxItems: 2
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iommus:
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maxItems: 1
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clock-names
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- clocks
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unevaluatedProperties: false
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allOf:
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- $ref: spi-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: xlnx,zynqmp-qspi-1.0
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then:
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properties:
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reg:
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minItems: 2
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else:
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properties:
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reg:
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maxItems: 1
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examples:
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- |
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#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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qspi: spi@ff0f0000 {
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compatible = "xlnx,zynqmp-qspi-1.0";
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clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
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clock-names = "ref_clk", "pclk";
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interrupts = <0 15 4>;
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interrupt-parent = <&gic>;
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reg = <0x0 0xff0f0000 0x0 0x1000>,
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<0x0 0xc0000000 0x0 0x8000000>;
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};
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};
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