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Having interrupts events and FIFO available allows to evaluate the sensor events. Cover the list of interrupt based sensor events. Keep them in the header file for readability. Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com> Link: https://patch.msgid.link/20241228232949.72487-5-l.rubusch@gmail.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
125 lines
3.7 KiB
C
125 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* ADXL345 3-Axis Digital Accelerometer
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*
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* Copyright (c) 2017 Eva Rachel Retuya <eraretuya@gmail.com>
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*/
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#ifndef _ADXL345_H_
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#define _ADXL345_H_
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#define ADXL345_REG_DEVID 0x00
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#define ADXL345_REG_THRESH_TAP 0x1D
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#define ADXL345_REG_OFSX 0x1E
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#define ADXL345_REG_OFSY 0x1F
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#define ADXL345_REG_OFSZ 0x20
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#define ADXL345_REG_OFS_AXIS(index) (ADXL345_REG_OFSX + (index))
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/* Tap duration */
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#define ADXL345_REG_DUR 0x21
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/* Tap latency */
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#define ADXL345_REG_LATENT 0x22
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/* Tap window */
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#define ADXL345_REG_WINDOW 0x23
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/* Activity threshold */
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#define ADXL345_REG_THRESH_ACT 0x24
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/* Inactivity threshold */
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#define ADXL345_REG_THRESH_INACT 0x25
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/* Inactivity time */
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#define ADXL345_REG_TIME_INACT 0x26
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/* Axis enable control for activity and inactivity detection */
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#define ADXL345_REG_ACT_INACT_CTRL 0x27
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/* Free-fall threshold */
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#define ADXL345_REG_THRESH_FF 0x28
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/* Free-fall time */
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#define ADXL345_REG_TIME_FF 0x29
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/* Axis control for single tap or double tap */
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#define ADXL345_REG_TAP_AXIS 0x2A
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/* Source of single tap or double tap */
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#define ADXL345_REG_ACT_TAP_STATUS 0x2B
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/* Data rate and power mode control */
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#define ADXL345_REG_BW_RATE 0x2C
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#define ADXL345_REG_POWER_CTL 0x2D
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#define ADXL345_REG_INT_ENABLE 0x2E
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#define ADXL345_REG_INT_MAP 0x2F
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#define ADXL345_REG_INT_SOURCE 0x30
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#define ADXL345_REG_INT_SOURCE_MSK 0xFF
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#define ADXL345_REG_DATA_FORMAT 0x31
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#define ADXL345_REG_XYZ_BASE 0x32
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#define ADXL345_REG_DATA_AXIS(index) \
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(ADXL345_REG_XYZ_BASE + (index) * sizeof(__le16))
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#define ADXL345_REG_FIFO_CTL 0x38
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#define ADXL345_FIFO_CTL_SAMPLES_MSK GENMASK(4, 0)
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/* 0: INT1, 1: INT2 */
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#define ADXL345_FIFO_CTL_TRIGGER_MSK BIT(5)
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#define ADXL345_FIFO_CTL_MODE_MSK GENMASK(7, 6)
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#define ADXL345_REG_FIFO_STATUS 0x39
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#define ADXL345_REG_FIFO_STATUS_MSK 0x3F
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#define ADXL345_INT_OVERRUN BIT(0)
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#define ADXL345_INT_WATERMARK BIT(1)
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#define ADXL345_INT_FREE_FALL BIT(2)
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#define ADXL345_INT_INACTIVITY BIT(3)
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#define ADXL345_INT_ACTIVITY BIT(4)
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#define ADXL345_INT_DOUBLE_TAP BIT(5)
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#define ADXL345_INT_SINGLE_TAP BIT(6)
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#define ADXL345_INT_DATA_READY BIT(7)
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/*
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* BW_RATE bits - Bandwidth and output data rate. The default value is
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* 0x0A, which translates to a 100 Hz output data rate
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*/
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#define ADXL345_BW_RATE GENMASK(3, 0)
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#define ADXL345_BW_LOW_POWER BIT(4)
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#define ADXL345_BASE_RATE_NANO_HZ 97656250LL
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#define ADXL345_POWER_CTL_STANDBY 0x00
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#define ADXL345_POWER_CTL_WAKEUP GENMASK(1, 0)
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#define ADXL345_POWER_CTL_SLEEP BIT(2)
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#define ADXL345_POWER_CTL_MEASURE BIT(3)
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#define ADXL345_POWER_CTL_AUTO_SLEEP BIT(4)
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#define ADXL345_POWER_CTL_LINK BIT(5)
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/* Set the g range */
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#define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0)
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/* Data is left justified */
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#define ADXL345_DATA_FORMAT_JUSTIFY BIT(2)
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/* Up to 13-bits resolution */
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#define ADXL345_DATA_FORMAT_FULL_RES BIT(3)
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#define ADXL345_DATA_FORMAT_SPI_3WIRE BIT(6)
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#define ADXL345_DATA_FORMAT_SELF_TEST BIT(7)
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#define ADXL345_DATA_FORMAT_2G 0
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#define ADXL345_DATA_FORMAT_4G 1
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#define ADXL345_DATA_FORMAT_8G 2
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#define ADXL345_DATA_FORMAT_16G 3
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#define ADXL345_DEVID 0xE5
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#define ADXL345_FIFO_SIZE 32
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/*
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* In full-resolution mode, scale factor is maintained at ~4 mg/LSB
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* in all g ranges.
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*
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* At +/- 16g with 13-bit resolution, scale is computed as:
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* (16 + 16) * 9.81 / (2^13 - 1) = 0.0383
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*/
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#define ADXL345_USCALE 38300
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/*
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* The Datasheet lists a resolution of Resolution is ~49 mg per LSB. That's
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* ~480mm/s**2 per LSB.
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*/
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#define ADXL375_USCALE 480000
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struct adxl345_chip_info {
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const char *name;
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int uscale;
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};
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int adxl345_core_probe(struct device *dev, struct regmap *regmap,
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bool fifo_delay_default,
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int (*setup)(struct device*, struct regmap*));
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#endif /* _ADXL345_H_ */
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