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22b6c9e8fe
This patch adds support for advanced features supported by the Noise-Aware PLL of Maxwell. Glitchless switch allows the PL field to be updated without disabling the PLL first if the SYNC_MODE bit of the CFG register is set. More significantly, DFS allows the PLL to monitor the actual input voltage and to dynamically lower the output frequency accordingly. This allows the clock to be more tolerant of lower voltages. These improvements are only supported for Tegra speedos >= 1. Also add the voltage table that is suitable for GM20B's NAPLL. This change needs to be done atomically for the right voltages to be used by the clock driver. v2. Fix build on non-Tegra platforms Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
93 lines
3.4 KiB
C
93 lines
3.4 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include "gk20a.h"
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#include <core/tegra.h>
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const struct cvb_coef gm20b_cvb_coef[] = {
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/* KHz, c0, c1, c2 */
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/* 76800 */ { 1786666, -85625, 1632 },
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/* 153600 */ { 1846729, -87525, 1632 },
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/* 230400 */ { 1910480, -89425, 1632 },
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/* 307200 */ { 1977920, -91325, 1632 },
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/* 384000 */ { 2049049, -93215, 1632 },
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/* 460800 */ { 2122872, -95095, 1632 },
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/* 537600 */ { 2201331, -96985, 1632 },
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/* 614400 */ { 2283479, -98885, 1632 },
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/* 691200 */ { 2369315, -100785, 1632 },
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/* 768000 */ { 2458841, -102685, 1632 },
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/* 844800 */ { 2550821, -104555, 1632 },
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/* 921600 */ { 2647676, -106455, 1632 },
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};
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static const struct cvb_coef gm20b_na_cvb_coef[] = {
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/* KHz, c0, c1, c2, c3, c4, c5 */
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/* 76800 */ { 814294, 8144, -940, 808, -21583, 226 },
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/* 153600 */ { 856185, 8144, -940, 808, -21583, 226 },
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/* 230400 */ { 898077, 8144, -940, 808, -21583, 226 },
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/* 307200 */ { 939968, 8144, -940, 808, -21583, 226 },
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/* 384000 */ { 981860, 8144, -940, 808, -21583, 226 },
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/* 460800 */ { 1023751, 8144, -940, 808, -21583, 226 },
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/* 537600 */ { 1065642, 8144, -940, 808, -21583, 226 },
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/* 614400 */ { 1107534, 8144, -940, 808, -21583, 226 },
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/* 691200 */ { 1149425, 8144, -940, 808, -21583, 226 },
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/* 768000 */ { 1191317, 8144, -940, 808, -21583, 226 },
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/* 844800 */ { 1233208, 8144, -940, 808, -21583, 226 },
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/* 921600 */ { 1275100, 8144, -940, 808, -21583, 226 },
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/* 998400 */ { 1316991, 8144, -940, 808, -21583, 226 },
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};
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const u32 speedo_to_vmin[] = {
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/* 0, 1, 2, 3, 4, */
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950000, 840000, 818750, 840000, 810000,
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};
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int
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gm20b_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt)
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{
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struct nvkm_device_tegra *tdev = device->func->tegra(device);
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struct gk20a_volt *volt;
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u32 vmin;
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if (tdev->gpu_speedo_id >= ARRAY_SIZE(speedo_to_vmin)) {
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nvdev_error(device, "unsupported speedo %d\n",
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tdev->gpu_speedo_id);
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return -EINVAL;
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}
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volt = kzalloc(sizeof(*volt), GFP_KERNEL);
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if (!volt)
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return -ENOMEM;
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*pvolt = &volt->base;
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vmin = speedo_to_vmin[tdev->gpu_speedo_id];
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if (tdev->gpu_speedo_id >= 1)
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return gk20a_volt_ctor(device, index, gm20b_na_cvb_coef,
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ARRAY_SIZE(gm20b_na_cvb_coef), vmin, volt);
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else
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return gk20a_volt_ctor(device, index, gm20b_cvb_coef,
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ARRAY_SIZE(gm20b_cvb_coef), vmin, volt);
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}
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