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In QAT GEN4 devices, the compression slice count was tracked using the dcpr_cnt field. Introduce a new cpr_cnt field in the rate limiting (RL) infrastructure to track the compression (CPR) slice count independently. The cpr_cnt value is populated via the RL_INIT admin message. The existing dcpr_cnt field will now be used exclusively to cache the decompression slice count, ensuring a clear separation between compression and decompression tracking. Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
99 lines
3.0 KiB
C
99 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2023 Intel Corporation */
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#include <linux/dma-mapping.h>
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#include <linux/pci.h>
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#include "adf_admin.h"
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#include "adf_accel_devices.h"
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#include "adf_rl_admin.h"
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static void
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prep_admin_req_msg(struct rl_sla *sla, dma_addr_t dma_addr,
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struct icp_qat_fw_init_admin_sla_config_params *fw_params,
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struct icp_qat_fw_init_admin_req *req, bool is_update)
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{
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req->cmd_id = is_update ? ICP_QAT_FW_RL_UPDATE : ICP_QAT_FW_RL_ADD;
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req->init_cfg_ptr = dma_addr;
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req->init_cfg_sz = sizeof(*fw_params);
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req->node_id = sla->node_id;
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req->node_type = sla->type;
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req->rp_count = sla->ring_pairs_cnt;
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req->svc_type = sla->srv;
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}
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static void
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prep_admin_req_params(struct adf_accel_dev *accel_dev, struct rl_sla *sla,
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struct icp_qat_fw_init_admin_sla_config_params *fw_params)
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{
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fw_params->pcie_in_cir =
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adf_rl_calculate_pci_bw(accel_dev, sla->cir, sla->srv, false);
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fw_params->pcie_in_pir =
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adf_rl_calculate_pci_bw(accel_dev, sla->pir, sla->srv, false);
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fw_params->pcie_out_cir =
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adf_rl_calculate_pci_bw(accel_dev, sla->cir, sla->srv, true);
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fw_params->pcie_out_pir =
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adf_rl_calculate_pci_bw(accel_dev, sla->pir, sla->srv, true);
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fw_params->slice_util_cir =
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adf_rl_calculate_slice_tokens(accel_dev, sla->cir, sla->srv);
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fw_params->slice_util_pir =
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adf_rl_calculate_slice_tokens(accel_dev, sla->pir, sla->srv);
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fw_params->ae_util_cir =
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adf_rl_calculate_ae_cycles(accel_dev, sla->cir, sla->srv);
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fw_params->ae_util_pir =
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adf_rl_calculate_ae_cycles(accel_dev, sla->pir, sla->srv);
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memcpy(fw_params->rp_ids, sla->ring_pairs_ids,
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sizeof(sla->ring_pairs_ids));
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}
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int adf_rl_send_admin_init_msg(struct adf_accel_dev *accel_dev,
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struct rl_slice_cnt *slices_int)
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{
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struct icp_qat_fw_init_admin_slice_cnt slices_resp = { };
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int ret;
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ret = adf_send_admin_rl_init(accel_dev, &slices_resp);
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if (ret)
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return ret;
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slices_int->dcpr_cnt = slices_resp.dcpr_cnt;
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slices_int->pke_cnt = slices_resp.pke_cnt;
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/* For symmetric crypto, slice tokens are relative to the UCS slice */
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slices_int->cph_cnt = slices_resp.ucs_cnt;
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slices_int->cpr_cnt = slices_resp.cpr_cnt;
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return 0;
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}
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int adf_rl_send_admin_add_update_msg(struct adf_accel_dev *accel_dev,
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struct rl_sla *sla, bool is_update)
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{
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struct icp_qat_fw_init_admin_sla_config_params *fw_params;
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struct icp_qat_fw_init_admin_req req = { };
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dma_addr_t dma_addr;
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int ret;
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fw_params = dma_alloc_coherent(&GET_DEV(accel_dev), sizeof(*fw_params),
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&dma_addr, GFP_KERNEL);
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if (!fw_params)
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return -ENOMEM;
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prep_admin_req_params(accel_dev, sla, fw_params);
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prep_admin_req_msg(sla, dma_addr, fw_params, &req, is_update);
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ret = adf_send_admin_rl_add_update(accel_dev, &req);
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dma_free_coherent(&GET_DEV(accel_dev), sizeof(*fw_params), fw_params,
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dma_addr);
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return ret;
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}
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int adf_rl_send_admin_delete_msg(struct adf_accel_dev *accel_dev, u16 node_id,
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u8 node_type)
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{
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return adf_send_admin_rl_delete(accel_dev, node_id, node_type);
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}
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