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af1825d766
Convert the actions,s900-pinctrl binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
220 lines
7.7 KiB
YAML
220 lines
7.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/actions,s900-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Actions Semi S900 Pin Controller
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maintainers:
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- Manivannan Sadhasivam <mani@kernel.org>
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properties:
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compatible:
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const: actions,s900-pinctrl
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reg:
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maxItems: 1
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interrupts:
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maxItems: 6
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description: The interrupt outputs from the controller. There is one GPIO
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interrupt per GPIO bank. The number of interrupts listed depends on the
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number of GPIO banks on the SoC. The interrupts must be ordered by bank,
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starting with bank 0.
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interrupt-controller: true
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"#interrupt-cells":
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const: 2
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clocks:
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maxItems: 1
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gpio-controller: true
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gpio-line-names:
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maxItems: 146
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gpio-ranges: true
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"#gpio-cells":
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const: 2
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-controller
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- "#interrupt-cells"
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- clocks
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- gpio-controller
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- gpio-ranges
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- "#gpio-cells"
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additionalProperties:
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type: object
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description: Pin configuration subnode
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additionalProperties: false
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properties:
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pinmux:
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type: object
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description: Pin mux configuration
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$ref: /schemas/pinctrl/pinmux-node.yaml#
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additionalProperties: false
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properties:
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groups:
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items:
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enum: [
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lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp,
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sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp,
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rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp,
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rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp,
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i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp, pcm1_clk_mfp,
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pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp, eram_a7_mfp, eram_a8_mfp,
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eram_a9_mfp, eram_a10_mfp, eram_a11_mfp, lvds_oep_odn_mfp,
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lvds_ocp_obn_mfp, lvds_oap_oan_mfp, lvds_e_mfp,
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spi0_sclk_mosi_mfp, spi0_ss_mfp, spi0_miso_mfp, uart2_rtsb_mfp,
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uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp,
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sd0_d1_mfp, sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp,
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sd0_clk_mfp, sd1_cmd_clk_mfp, uart0_rx_mfp, nand0_d0_ceb3_mfp,
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uart0_tx_mfp, i2c0_mfp, csi0_cn_cp_mfp, csi0_dn0_dp3_mfp,
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csi1_dn0_cp_mfp, dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp,
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nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp,
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csi1_dn0_dp0_mfp, uart4_rx_tx_mfp
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]
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function:
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items:
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enum: [
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eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
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uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
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pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0,
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sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds,
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usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0,
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nand1, spdif, sirq0, sirq1, sirq2
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]
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required:
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- groups
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- function
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pinconf:
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type: object
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description: Pin configuration parameters
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allOf:
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- $ref: /schemas/pinctrl/pincfg-node.yaml#
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- $ref: /schemas/pinctrl/pinmux-node.yaml#
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additionalProperties: false
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properties:
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groups:
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items:
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enum: [
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# pin groups for drive strength
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sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv, rmii_tx_d0_d1_drv,
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rmii_txen_rxer_drv, rmii_crs_dv_drv, rmii_rx_d1_d0_drv,
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rmii_ref_clk_drv, rmii_mdc_mdio_drv, sirq_0_1_drv, sirq2_drv,
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i2s_d0_d1_drv, i2s_lr_m_clk0_drv, i2s_blk1_mclk1_drv,
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pcm1_in_out_drv, lvds_oap_oan_drv, lvds_oep_odn_drv,
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lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv, sd1_d3_d0_drv,
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sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv, spi0_ss_miso_drv,
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uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv, uart3_drv, i2c0_drv,
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i2c1_drv, i2c2_drv, sensor0_drv,
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# pin groups for slew rate
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sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr,
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rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr,
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rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr,
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i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr,
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pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr,
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spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr,
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uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr,
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sensor0_sr
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]
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pins:
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items:
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enum: [
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eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv, eth_rxd1,
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eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio, sirq0, sirq1, sirq2,
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i2s_d0, i2s_bclk0, i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1,
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i2s_lrclk1, i2s_mclk1, pcm1_in, pcm1_clk, pcm1_sync, pcm1_out,
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eram_a5, eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11,
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lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp, lvds_ocn,
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lvds_obp, lvds_obn, lvds_oap, lvds_oan, lvds_eep, lvds_een,
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lvds_edp, lvds_edn, lvds_ecp, lvds_ecn, lvds_ebp, lvds_ebn,
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lvds_eap, lvds_ean, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0,
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sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
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spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx, uart0_tx,
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uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx,
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uart3_rtsb, uart3_ctsb, uart4_rx, uart4_tx, i2c0_sclk, i2c0_sdata,
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i2c1_sclk, i2c1_sdata, i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0,
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csi0_dn1, csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2,
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csi0_dn3, csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp,
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dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk,
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csi1_dn0, csi1_dp0, csi1_dn1, csi1_dp1, csi1_cn, csi1_cp,
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sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3, nand0_d4,
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nand0_d5, nand0_d6, nand0_d7, nand0_dqs, nand0_dqsn, nand0_ale,
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nand0_cle, nand0_ceb0, nand0_ceb1, nand0_ceb2, nand0_ceb3,
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nand1_d0, nand1_d1, nand1_d2, nand1_d3, nand1_d4, nand1_d5,
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nand1_d6, nand1_d7, nand1_dqs, nand1_dqsn, nand1_ale, nand1_cle,
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nand1_ceb0, nand1_ceb1, nand1_ceb2, nand1_ceb3, sgpio0, sgpio1,
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sgpio2, sgpio3
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]
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bias-bus-hold: true
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bias-high-impedance: true
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bias-pull-down:
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type: boolean
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bias-pull-up:
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type: boolean
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input-schmitt-enable: true
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input-schmitt-disable: true
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slew-rate: true
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drive-strength: true
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oneOf:
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- required:
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- groups
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- required:
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- pins
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl: pinctrl@e01b0000 {
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compatible = "actions,s900-pinctrl";
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reg = <0xe01b0000 0x1000>;
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clocks = <&cmu 1>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 0 146>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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uart2-default {
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pinmux {
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groups = "lvds_oep_odn_mfp";
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function = "uart2";
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};
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pinconf {
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groups = "lvds_oep_odn_drv";
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drive-strength = <12>;
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};
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};
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};
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